CLK2

PLLLOCK

CLK2C

T0003-01

PHSTR

DA[15:0]

DB[15:0]

PLLLOCK

DAC1

CLK2

CLK2C

th(PHSTR)

1/fPLLLOCK = N/fCLK2

ts(PHSTR)

td(CLK)

th

ts

T0004−01

DAC5686

www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009

Figure 37. Four Possible PLLLOCK Phases for N = 4 in External Clock Mode

To synchronize PLLLOCK input clocks across multiple DAC5686 chips, a synchronization signal on the PHSTR

pin is used. During configuration of the DAC5686 chips, address sync_phstr in config_msb is set high to

enable the PHSTR input pin as a synchronization input to the clock dividers generating the input clock. A

simultaneous low-to-high transition on the PHSTR pin for each DAC5686 then forces the input clock on

PLLLOCK to start in phase on each DAC. See Figure 38.

Figure 38. Using PHSTR to Synchronize PLLLOCK Input Clock for Multiple DACs in External Clock Mode

Copyright © 2003–2009, Texas Instruments Incorporated

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Product Folder Link(s): DAC5686