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STA326 数据表(PDF) 9 Page - STMicroelectronics |
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STA326 数据表(HTML) 9 Page - STMicroelectronics |
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9 / 64 page  DocID11531 Rev 9 9/64 STA326 Description 64 1.1 EQ processing Two channels of input data (re-sampled if necessary) at 96 kHz are provided to the EQ processing block. In this block, up to four user-defined biquads can be applied to each of the two channels. Prescaling, DC-blocking, high-pass, de-emphasis, bass, and tone control filters can also be applied based on various configuration parameter settings. The entire EQ block can be bypassed for all channels simultaneously by setting the DSPB bit to 1. And the CxEQBP bits can be used to bypass the EQ function on a per channel basis. Figure 3 shows the internal signal flow through the EQ block. Figure 3. Channel signal flow through the EQ block 1.2 Output configurations Figure 4. Output power-stage configurations 2-channel (full-bridge) configuration, register bits OCFG[1:0] = 00 2.1-channel configuration, register bits OCFG[1:0] = 01 1-channel mono-parallel configuration, register bits OCFG[1:0] = 11 The setup register is Configuration register F (addr 0x05) on page 34 Obsolete Product(s) - Obsolete Product(s) |
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