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STA326 数据表(PDF) 29 Page - STMicroelectronics |
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STA326 数据表(HTML) 29 Page - STMicroelectronics |
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29 / 64 page ![]() DocID11531 Rev 9 29/64 STA326 Register description 64 7.3 Configuration register C (addr 0x02) 7.3.1 DDX® power output mode The DDX® power output mode selects how the DDX® output timing is configured. Different power devices can use different output modes. The recommended use is OM = 10. When OM = 11 the CSZ bits determine the size of the DDX® compensating pulse. 7.3.2 DDX® variable compensating pulse size The DDX® variable compensating pulse size is intended to adapt to different power stage ICs. Contact ST for support when deciding this function. D7 D6 D5 D4 D3 D2 D1 D0 Reserved CSZ4 CSZ3 CSZ2 CSZ1 CSZ0 OM1 OM0 1 1 0000 1 0 Table 22. DDX® power output mode Bit R/W RST Name Description 1:0 RW 10 OM[1:0] DDX® power output mode: Selects configuration of DDX® output Table 23. DDX® output modes OM[1,0] Output stage - mode 00 Not used 01 Not used 10 Recommended 11 Variable compensation Table 24. DDX® compensating pulse CSZ[4:0] Compensating pulse size 00000 0 clock period compensating pulse size 00001 1 clock period compensating pulse size …… 10000 16 clock period compensating pulse size …… 11111 31 clock period compensating pulse size Obsolete Product(s) - Obsolete Product(s) |
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