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M41TC8025CMC7F 数据表(PDF) 10 Page - STMicroelectronics |
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M41TC8025CMC7F 数据表(HTML) 10 Page - STMicroelectronics |
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10 / 41 page ![]() Operation M41TC8025 10/41 DocID022873 Rev 4 2.2.5 Acknowledge Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case the transmitter must leave the data line high to enable the master to generate the STOP condition. Figure 5. Serial bus transfer sequence Figure 6. Acknowledgement sequence Obsolete Product(s) - Obsolete Product(s) |
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