Operation

M41TC8025

22/41

DocID022873 Rev 4

Figure 13. Fixed-cycle timer interrupt timing sequence

1. When the TE bit is set to 1, the fixed-cycle internal timer starts incrementing from 000h towards the target

value set in register 0Bh and 0Ch.

2. When the internal timer value reaches the target value, an interrupt event occurs. After the interrupt event,

the internal timer automatically counts starting from 000h towards the target value again.

3. When a fixed-cycle timer interrupt event occurs, the TF bit is set to 1.

4. Once the TF bit is set to 1, it remains until it is reset to 0 by the user.

5. If TIE=1 when a fixed-cycle timer interrupt occurs, the IRQ pin output is driven low. If TIE=0 when a fixed-

cycle timer interrupt event occurs, the IRQ pin output remains Hi-Z.

6. Output from the IRQ pin remains low during the tRTN period following each event, after which it is

automatically released to Hi-Z. The IRQ pin is again driven low when the next interrupt occurs.

7. When the TE bit is reset to 0, the fixed-cycle timer function is stopped and the IRQ pin is released to Hi-Z

immediately.

8. If the IRQ pin is low, the IRQ pin status is released to Hi-Z immediately when the TF bit value changes from

1 to 0.

9. If the IRQ pin is low, the IRQ pin status is released to Hi-Z immediately when the TIE bit value changes

from 1 to 0.

2.7

Time update interrupt function

The time update interrupt function generates periodic interrupts at one-second or one-

minute intervals according to the timing of the internal clock.

When a time update is generated, the IRQ pin will be pulled low if enabled (bit UIE=1) and

the flag bit (UF) will be set to 1 to indicate the time update occurrence. After the IRQ pin is

pulled low, it will be automatically released (change to Hi-Z) after time tRTN so that periodic

interrupts can be generated even if the user does not clear the flag bit.

The time update interrupt function related registers are given in Table 17.

Obsolete

Product(s)

- Obsolete

Product(s)