M41TC8025CMC7F datasheet(19/41 Pages) STMICROELECTRONICS

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DocID022873 Rev 4

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M41TC8025

Operation

timer value reaches the interrupt trigger value, a fixed-cycle interrupt will be triggered and

the timer will automatically start to count from 000h towards the interrupt trigger value again.

The TF bit in register 0Eh is the fixed-cycle timer interrupt flag. Once the timer is enabled

(TE=1) and the internal counter increment reaches the interrupt trigger value, the TF bit is

set to 1 to indicate a fixed-cycle timer interrupt occurrence. Once TF=1, it will not be

automatically cleared and relies on the user to reset to 0. Resetting the TF bit to 0 will

release the IRQ pin from low to Hi-Z immediately, otherwise the IRQ pin is auto-released

after time tRTN specified in Table 15.

The TIE bit in register 0Fh is the interrupt enable bit. If the interrupt is enabled (TIE=1) and

there is a fixed-cycle interrupt event, the IRQ pin will be pulled low. If the interrupt is disabled

(TIE=0), even if there is a fixed-cycle interrupt event, the IRQ pin will remain unchanged and

stay Hi-Z. The TF bit still can be set to 1, regardless of the status of the IRQ pin. Resetting

the TIE bit to 0 while IRQ is low will immediately release the IRQ pin (change to Hi-Z).

The TSEL1 and TSEL0 bits in register 0Dh are used to select the internal timer counting

source clock. Table 15 shows the configuration.

Note:

The IRQ pin auto release time (tRTN) varies according to the source clock selection.

When the source clock has been selected to "second update" or "minute update", the timing

of both counting and interrupts is coordinated with the clock update timing.

When the RESET bit in control register 0Fh is 1, the clock divider <4 KHz is stopped. As a

result, the fixed-cycle timer interrupt with source clocks of 64 Hz, 1 Hz and "minute" update

will be stopped.

Table 15. Timer source clock configuration

TSEL1

TSEL0

Clock source

Auto reset time

(tRTN)

Effect of RESET bit

4096 Hz (once per 244.14 μs)

122 μs

Not affected

64 Hz (once per 15.625 ms)

7.8125 ms

Does not operate

when RESET = 1

1 Hz (once per second)

7.8125 ms

“minute” update (once per minute)

7.8125 ms

Obsolete

Product(s)

- Obsolete

Product(s)

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