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LP5569 数据表(PDF) 3 Page - Texas Instruments |
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LP5569 数据表(HTML) 3 Page - Texas Instruments |
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3 / 93 page  1 C2+ 18 LED1 2 C1+ 17 LED2 3 VIN 16 LED3 4 AGND 15 LED4 5 EN/PWM 14 LED5 6 CLK 13 LED6 Not to scale Thermal Pad 3 LP5569 www.ti.com SNVSAP8A – JULY 2017 – REVISED SEPTEMBER 2017 Product Folder Links: LP5569 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 5 Device Comparison Table PART NUMBER GROUP I2C SLAVE ADDRESS LP5569 0 32h–35h and 40h (see I2C Slave Addressing) LP5569A 1 42h–45h and 40h (see I2C Slave Addressing) 6 Pin Configuration and Functions RTW Package 24-Pin WQFN With Exposed Thermal Pad Top View (1) A: analog pin; G: ground pin; P: power pin; I: input pin; OD: open-drain output pin Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. ADDR 20 I I2C slave-address selection pin. See I2C Slave Addressing for more details. This pin must not be left floating. AGND 4 G Analog and digital ground. Connect to PGND, exposed thermal pad, and common ground plane. C1– 24 A Negative pin of charge-pump flying capacitor 1. If charge pump is not used, this pin must be left floating. C1+ 2 A Positive pin of charge-pump flying capacitor 1. If charge pump is not used, this pin must be left floating. C2– 23 A Negative pin of charge-pump flying capacitor 2. If charge pump is not used, this pin must be left floating. C2+ 1 A Positive pin of charge-pump flying capacitor 2. If charge pump is not used, this pin must be left floating. CLK 6 I, OD Clock input/output. By default this pin is a clock input. If not used, this pin must be connected to GND or VIN. EN/PWM 5 I Chip enable and PWM input pin. |
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