LS Gate

13

4

3

2

VGG DIS

FLT

SRE Mode

SRE

10

PWM

12

AGND

11

9

RDLY

19

HS Gate

20

SW

18

BST

8

7

15

17

14

CSP

CSN

VGG

PGND

1

HS Sense

Thermal

Sense

BP3

5

IMON

6

ILIM

Bias + V

GG

Generator

16

Vin

Digital Control

UVLO

Blanking

Control

G = 50

UCD7232

0.5 V

HS Fault

OC Fault

TSD

PP

PAD

UCD7232

SLUSAH3

– MAY 2011

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION (CONTINUED)

An on-chip temperature sense monitors the die temperature. If it exceeds approximately 165

°C, the temperature

sensor will initiate a thermal shutdown that halts output switching and sets the FLT flag. The temperature fault

automatically clears when the die temperatures falls by approximately 20

°.

FUNCTIONAL BLOCK DIAGRAM

Figure 1. UCD7232 Block Diagram

2

Copyright

© 2011, Texas Instruments Incorporated