UCD7232

www.ti.com

SLUSAH3

– MAY 2011

INPUT AND OUTPUT CAPACITORS

At the drain of the high-side FET, current is drawn in fast, brief, rectangular pulses. It is important to provide low

impedance, high frequency energy storage right at the drain of the FET. For this 20A power stage, two 22

µF,

16V or 25V ceramic capacitors are recommended. C1 and C2 should be placed as close to the drain of Q1 as

possible. The ground side of the capacitors should be connected as close as possible to the source lead of Q2. If

designing a multiphase power supply, these capacitors should be present at each power stage. Bulk input

bypass capacitance may also be required to minimize voltage variations during transient loads. This bulk

capacitance is not shown on Figure 7, but it is typically required. Bulk capacitance can be shared among multiple

power stages.

The inductor ripple current must be absorbed by the output capacitors. The ripple current is triangular in shape

and contains significant energy at the switching frequency and its harmonics. To keep the ripple voltage

amplitude to a minimum, low ESR and low ESL capacitors must be used. Multilayer ceramic capacitors are ideal

devices. While bulk capacitance is also required to provide energy storage during transient events, the bulk

capacitors do not typically handle much ripple current because their higher ESL and ESR make them look

inductive at the ripple frequencies.

The output ripple voltage is directly proportional to the inductor ripple current. The inductor ripple current varies

widely with input voltage and duty cycle. That makes it difficult to come up with a one-size-fits-all

recommendation for the proper amount of ceramic output capacitance. A good starting point is approximately

100

µF. In this design two 47µF capacitors are used (C7 and C8). These capacitors should be placed close to the

inductor, L1, and the ground side of these caps should be connected as close as possible to the source lead of

the low-side FET, Q2.

Bulk capacitance is used not only for short term transient energy storage, but also as a frequency response

tailoring element in the power supply feedback loop. Several hundred microfarads, at a minimum, are commonly

used in a power stage of this current capability. In this example, 330

µF is being used (C9). More capacitance

may be required depending on the transient response requirements of the load.

BYPASS AND BOOTSTRAP CAPACITORS

In this design, the bypass capacitors on BP3 (C12), VGG (C4), and the bootstrap capacitor (C3) use the

recommended values. A high frequency 0.1

µF bypass capacitor, C11, has also been added at the Vin pin of the

UCD7232. This cap attenuates the high frequency noise that is present on the Vin rail. It should be placed as

close as possible to pin 16 and connect to analog ground with a short, direct trace.

LAYOUT RECOMMENDATIONS

Proper component placement and trace routing can have a significant impact on overall power stage efficiency

and reduce noise coupling into nearby circuits. The following are some key layout considerations.

•

Locate the driver as close as possible to the power FETs, but do not place it directly under either FET. The

driver is a power device and needs its own thermal cooling path. Clustering multiple hot parts too close

together can increase the risk of excessive temperature rise and potentially cause a thermal shutdown event.

•

Locate the VGG bypass and bootstrap capacitors as close as possible to the driver.

•

Pay special attention to the GND trace. The ground side of the input bypass capacitors, the ground side of

the output capacitors, the low-side FET source leads, and the PGND connection to the driver should

connected together in a tight

“single point” ground, using wide, low inductance traces and few, if any vias.

Use of a ground plane is strongly encouraged.

•

Connect the power-pad on the bottom of the driver to analog ground. The power-pad is not intended to be a

high current carrying connection. The analog ground and power ground should be connected together at one

point, near the AGND pin. Care should be taken to insure that heavy currents are not pulled through the

analog ground traces.

•

The switching node trace should be kept short and compact. This is the noisiest node in the system with high

dV/dt slew rates.

•

Use wide traces for the HS Gate and LS Gate signals closely following the associated switching node and

ground traces. Use 0.050

” to 0.080” (1.27 to 2.03 mm) wide traces if possible. Use at least two vias if the gate

drive trace has to be routed from one layer to another.

•

Keep the low level input and output traces away from the switching node. The high dV/dt signal present there

can induce significant noise into the relatively high impedance nodes. Pay particular attention to the routing of

the CSP and CSN traces.

Copyright

© 2011, Texas Instruments Incorporated

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