UCD7232

SLUSAH3

– MAY 2011

www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

VIN = 12V, 4.7 µF from VGG to PGND, 1 µF from BP3 to AGND, 0.22 µF from BST to SW, TA = TJ = –40°C to 125°C,

RDLY = 8.06k

Ω, SRE Mode = 3.3V, VGG DIS tied to AGND (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V(ILIM) = 1.50 V, (CSP – CSN) = 20 mV,

Fault detection time. Delay until FLT

tFAULT_FLT

85

170

ns

asserted(2)

CSN = 1.80 V

PWM falling to FLT falling after a current limit event is

Propagation delay from PWM to reset FLT(2)

85

200

ns

cleared. PWM pulse width

≥100 ns.

CURRENT SENSE BLANKING (RDLY, HS Sense)

IRDLY

RDLY source current

8.06 k

Ω resistor from RDLY to AGND

80

90

100

µA

RDLY resistance range(2)

7.5

8.06

10

k

Ω

RDLY = 8.06 k

Ω. From SW rising to HS fault comparator

tBLANK

HS blanking time

110

125

140

ns

enabled

IHS Sense

HS Sense sink current

RHS Sense = 2. kΩ to VIN, VIN = 12 V

100

µA

HS fault detection time. Delay after tBLANK

RDLY = 8.06 k

Ω, RHS Sense = 2 kΩ to VIN, VIN = 12 V,

tHSFAULT_HS

20

ns

until HS Gate falling(2)

VIN – VSW = 220 mV

HS fault detection time. Delay after tBLANK

RDLY = 8.06 k

Ω, RHS Sense = 2 kΩ to VIN, VIN = 12 V,

tHSFAULT_LS

30

ns

until LS Gate falling(2)

VIN – VSW = 220 mV

CURRENT SENSE AMPLIFER (IMON, CSP, CSN)

V(IMON) at no load

CSP = CSN = 1.8 V

460

500

540

mV

Closed loop DC gain

CSP

– CSN = 10 mV; 0.5 V ≤ CSN ≤ 3.3 V

48

50.2

52.4

V/V

Gain with 2.49k resistors in series with CSP, CSN

45.6

47.8

49.9

V/V

Input impedance(2)

Differential, CSP

– CSN

100

k

Ω

VCM

Input common mode voltage range(2)

VCM(max) is limited to (VGG – 1.2 V)

–0.3

5.6

V

V(IMON)MIN

CSP = 1.2 V; CSN = 1.3 V; I(IMON) = –250 µA

0.1

0.15

V

V(IMON)MAX

CSP = 1.3 V; CSN = 1.2 V; I(IMON) = 500 µA

3

3.2

3.3

V

Sampling Rate(2)

5

Msps

LOW-SIDE OUTPUT DRIVER (LS Gate)

Peak Source Current(2)

VGG = 6.2 V, PWM = Low, LS Gate = 3 V

6

A

Peak Sink Current (2)

VGG = 6.2 V, PWM = High, LS Gate = 3 V

6

A

tRL

Rise Time(2)

CL = 6 nF, VIN = 12 V, VGG = 6.2 V

30

ns

tFL

Fall Time(2)

CL = 6 nF, VIN = 12 V, VGG = 6.2 V

20

ns

Output with VGG <UVLO

(2)

VGG = 1 V, Isink = 10 mA

0

0.5

V

Propagation Delay from PWM to LS Gate(2)

CL = 3 nF, PWM falling SW = 0 V, VGG = 6.2 V

46

ns

HIGH-SIDE OUTPUT DRIVER (HS Gate)

VIN = 12 V, BST = 6.2 V, PWM = High,

Source current(2)

4

A

HS Gate = 3 V

VIN = 12 V, BST = 6.2 V, PWM = Low,

Sink current(2)

4

A

HS Gate = 3 V

tRH

Rise time(2)

CL = 3 nF HS Gate to SW, VGG = 6.2 V

27

ns

tFH

Fall time(2)

CL = 3 nF HS Gate to SW, VGG = 6.2 V

21

ns

CL = 3 nF HS Gate to SW, PWM rising,

Propagation delay from PWM to HS Gate(2)

50

ns

SW = 0 V, VGG = 6.2 V

SWITCHING TIME

tDLH

HS gate turn-off propagation delay(2)

CL = 3 nF

16

ns

tDLL

LS gate turn-off propagation delay(2)

CL = 3 nF

15

ns

tDTH

Dead time LS; Gate off to HS; Gate on(2)

CL = 3 nF

12

ns

tDTL

Dead time HS; Gate off to LS; Gate on(2)

CL = 3 nF

15

ns

BOOTSTRAP DIODE

VF

Forward voltage(2)

Forward bias current 100 mA

0.4

V

THERMAL SHUTDOWN

Rising threshold(2)

155

165

175

°C

Falling threshold(2)

135

145

155

°C

Hysteresis(2)

20

°C

(2)

As designed and characterized. Not 100% tested in production.

6

Copyright

© 2011, Texas Instruments Incorporated