BLANK

t

- 33

RDLY =

11.413

UCD7232

www.ti.com

SLUSAH3

– MAY 2011

RDLY

The RDLY pin sets the blanking time of the high-side fault detection comparator. A resistor to AGND sets the

blanking time according to the following formula, where tBLANK is in nanoseconds and RDLY is in kΩ. Values of

RDLY of greater than 25k

Ω should not be used.

(6)

To calculate the nominal blanking time for a given value of resistance, use the formula below.

tBLANK = 11.413 × RDLY + 33

(7)

The blanking interval begins on the rising edge of SW. During the blanking time the high-side fault comparator is

held off. A high-side fault is flagged when the voltage drop across the high-side FET exceeds the threshold set

by the HS Sense pin. Blanking is required because the high amplitude ringing that occurs on the rising edge of

SW would otherwise cause false triggering of the fault comparator. The required amount of blanking time is a

function of the high-side FET, the PCB layout, and whether or not a snubber network is being used. A value of

125ns is a typical starting point. An RDLY of 8.06k

Ω will provide 125ns of blanking. The blanking interval should

be kept as short as possible, consistent with reliable fault detection. The blanking interval sets the minimum duty

cycle pulse width where high-side fault detection is possible. When the duty cycle of the PWM pulses are

narrower than the blanking time, the high-side fault detection comparator is held off for the entire on-time and is,

therefore, blind to any high-side faults.

Internally, the RDLY pin is fed by a 90

µA current source. When using the default value of 8.06kΩ, the voltage

observed on the RDLY pin will be approximately 725mV.

HS SENSE

A resistor from the HS Sense pin to the drain of the high-side FET sets the high-side fault detection threshold.

When the high-side FET is on, the current flow in the FET produces a voltage drop across the device. The

magnitude of this voltage is equal to the RDS(ON) times the current through the FET. An absolute maximum

current level can be set during the design stage and the resultant voltage drop across the FET can be calculated.

This maximum voltage drop,

ΔVMAX, sets the high-side fault threshold.

Internally, a high speed comparator monitors the voltage between the SW pin and the HS Sense pin when the

high-side FET is on. Whenever the voltage on the SW pin is lower than the voltage on the HS Sense pin, a fault

is flagged. To prevent false tripping during the ringing that accompanies the rising edge of SW, the output of the

comparator is held off (blanked) for a time interval set by the RDLY pin. The voltage on the HS Sense pin is set

by a resistor connected from the pin to the high-side FET drain. The HS Sense resistor value is calculated from

the following formula, where

ΔVMAX is in mV, and RHS Sense is in kilohms.

RHS Sense = ΔVMAX / 100

(8)

For example, if

ΔVMAX is 100mV, then RHS Sense is 1kΩ.

The equation can be restated as follows, with RHS Sense in kilohms, RDS(ON) in milliohms, and IMAX in amps:

RHS Sense = RDS(ON)HOT × IMAX) / 100

(9)

The value of IMAX should be set to approximately 150% of the expected maximum steady-state current. This

allows some headroom to avoid nuisance fault events due to transient load currents and the inductor ripple

current. Also, keep in mind that the RDS(ON) of a FET has a large positive temperature coefficient of

approximately 4000ppm/

°C. The junction temperature of the FET will be elevated when operating at currents

near the IMAX threshold. In the equation above, use a value of RDS(ON)HOT that is approximately 140% of its typical

room temperature value. When using the internal VGG gate drive supply, the FET, when turned on, is driven to a

VGS enhancement voltage of approximately 6V. Most FET data sheets provide RDS(ON) values for VGS values of

4.5V and 10V. Do not use the VGS = 10V value for the room temperature RDS(ON) value. Some manufacturers

provide a graph of RDS(ON) vs VGS. If provided, use the VGS = 6V value for the room temperature RDS(ON) value.

A 100

µA current sink pulls current through RHS Sense. This sets up a reference voltage drop equal to ΔVMAX. It is

important to connect the far end of the RHS Sense resistor directly to the drain of the high-side FET. This should be

made with a separate, non-current-carrying trace. This insures that only the RDS(ON) of the FET influences the

fault threshold and not the resistance of the pc board traces.

Copyright

© 2011, Texas Instruments Incorporated

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