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TLV70436DBVT.A 数据表(PDF) 20 Page - Texas Instruments |
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TLV70436DBVT.A 数据表(HTML) 20 Page - Texas Instruments |
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20 / 33 page ![]() 8.4 Power Supply Recommendations The TLV704 is designed to operate from an input voltage supply range between 2.5 V and 24 V. The input voltage range must provide adequate headroom for the device to have a regulated output. Inductive impedances between the input supply and the IN pin can create significant voltage excursions at the IN pin during start-up or load transient events. If inductive impedances are unavoidable, use an input capacitor. 8.5 Layout 8.5.1 Layout Guidelines For best overall performance, place all circuit components on the same side of the printed-circuit-board and as near as practical to the respective LDO pin connections. Place ground return connections for the input and output capacitors as close to the GND pin as possible, using wide, component-side, copper planes. Do not use vias and long traces to create LDO circuit connections to the input capacitor, output capacitor, or the resistor divider because this practice negatively affects system performance. This grounding and layout scheme minimizes inductive parasitics, and thereby reduces load-current transients, minimizes noise, and increases circuit stability. A ground reference plane is also recommended and is either embedded in the PCB or located on the bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the output voltage and shield the LDO from noise. 8.5.1.1 Power Dissipation To provide reliable operation, worst-case junction temperature must not exceed 125°C. This restriction limits the power dissipation the regulator can handle in any given application. To make sure the junction temperature is within acceptable limits, calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than or equal to PD(max). The maximum-power-dissipation limit is determined using Equation 6: PDmax = TJmax− TA RθJA (6) where: • TJmax is the maximum allowable junction temperature • RθJA is the thermal resistance junction-to-ambient for the package (see the Thermal Informationtable) • TA is the ambient temperature The regulator dissipation is calculated using Equation 7: PD= VIN− VOUT ×IOUT (7) 8.5.2 Layout Example COUT VOUT V IN GND PLANE CIN Figure 8-11. Layout Example for the DBV Package TLV704 SBVS148F – SEPTEMBER 2010 – REVISED MARCH 2023 www.ti.com 20 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV704 |
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