TUSB1002AI datasheet(4/38 Pages) TI2

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Table 4-1. Pin Functions (continued)

TYPE

INTERNAL PULLUP

PULLDOWN

DESCRIPTION

NAME

NO.

CFG1

I (4-level)

PU (approx 45K)

PD (approx 95K)

CFG1. This pin along with CFG2 selects the VOD linearity range and DC gain for

both channels 1 and 2. The state of this pin is sampled after the rising edge of

EN. Refer to Figure 5-2 for details of timing. Refer to Table 6-3 for VOD linearity

range and DC gain options.

CFG2

I (4-level)

PU (approx 45K)

PD (approx 95K)

CFG2. This pin along with CFG1 sets the VOD linearity range and DC gain for

both channels 1 and 2. The state of this pin is sampled after the rising edge of

EN. Refer to Figure 5-2 for details of timing. Refer to Table 6-3 for VOD linearity

range and DC gain options.

MODE

I (4-level)

PU (approx 45 K)

PD (approx 95K)

MODE. This pin is for selecting different modes of operation. The state of this pin

is sampled after the rising edge of EN. Refer to Figure 5-2 for details of timing.

0 = Basic Redriver Mode.

R = PCIe / Test Mode. PCIe Mode and TI Internal use only

F = USB3.2 x1 Dual Channel Operation enabled (TUSB1002A normal mode).

1 = USB3.2 x1 Single-channel operation.

RSVD1

—

RSVD1. Under normal operation, this pin is driven low by TUSB1002A.

Recommend leaving this pin unconnected on PCB.

DCBOOST

I (2-level)

PU (approx 400 K)

DCBOOST#. This pin when asserted low increases the DC Gain level defined

inTable 6-3 by +1dB unless already at +2dB. If DC Gain level defined inTable 6-3

is already at +2dB, then asserting this pin low will not change the DC Gain level.

This pin can be left unconnected if this function is not needed.

1 = DC Gain defined by Table 6-3.

0 = DC Gain defined by Table 6-3 is increased by +1dB.

VCC

1, 13

Power

—

3.3V (±10%) Supply.

GND

6, 10, 18,

GND

—

Ground

Thermal pad

—

Thermal pad. Recommend connecting to a solid ground plane.

TUSB1002A

SLLSF63C – MARCH 2018 – REVISED JULY 2024

www.ti.com

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