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TUSB1002AI 数据表(PDF) 8 Page - Texas Instruments |
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TUSB1002AI 数据表(HTML) 8 Page - Texas Instruments |
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8 / 38 page  5.5 Electrical Characteristics (continued) over operating free-air temperature and voltage range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VTX-RCV-DETECT Amount of voltage change allowed during Rx Detection. Measured at package pins. 600 mV VTX-CM-IDLE-DELTA Transmitter idle common mode voltage change U2/U3 state. Max allowed instantaneous commode- mode voltage at connector side of AC coupling capacitor. This is an absolute voltage spec referenced to the receive side termination ground. -600 600 mV VTX-DC-CM TX DC common mode voltage 1200mVpp linear range setting; 0 1.85 2.05 V VTX-CM-AC-PP-ACTIVE Transmitter AC common mode peak-peak voltage in U0. Maximum mismatch from TXP+TXN for both time and amplitude. 1200mVpp linear setting; CHx_EQ setting matches input channel insertion loss; 116 mV VTX-IDLE-DIFF-AC-PP AC electrical idle differential peak-to-peak output voltage 0 10 mV VTX-CM-DC-ACTIVE- IDLE-DELTA Absolute DC common mode voltage between U1 and U0 200 mV RTX-DC-CM TX DC common mode impedance 18 30 Ω RTX-DC-DIFF TX DC differential impedance 72 120 Ω ITX-SHORT Transmitter short-circuit current limit. 107 mA CAC-COUPLING External AC coupling capacitor on differential pairs. 75 265 nF 5.6 Timing Requirements over operating free-air temperature and voltage range (unless otherwise noted) MIN NOM MAX UNIT td_pg Internal power good asserted high when VCC is at 2.5V 5 µs tCFG_SU CFG(1) pins setup before internal Reset(2) high 0 µs tCFG_HD CFG(1) pins hold after internal Reset(2) high 500 µs tVCC_RAMP VCC supply ramp requirement 0.1 50 ms (1) Following pins comprise CFG pins: MODE, CFG[2:1], CH1_EQ[2:1], CH2_EQ[2:1] (2) Internal reset is the logical AND of EN pin and internal power good. 5.7 Switching Characteristics over operating free-air temperature and voltage range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tIDLEEntry Delay from U0 to electrical idle VCC = 3.0V; EN = 1; See Figure 5-1 150 ps tIDLEEntry_U1 U1 exit time. Break in electrical idle to transmission of LFPS. VCC = 3.0V; EN = 1; See Figure 5-1 150 ps tIDLEEntry_U2U 3 U2/U3 exit time; Break in electrical idle to transmission of LFPS VCC = 3.0V; EN = 1; See Figure 5-1 6 µs tDIFF_DLY Differential propagation delay VCC = 3.0V; EN = 1; 150 ps tPWRUP_ACTIV E Time from assertion of EN to device active and performing Rx.Detect on both ports VCC = 3.0V; EN = 1; 8 ms tTX_RISE_FALL Transmitter rise/fall time VCC = 3.3V; EN = 1; 10Gbps; 20% to 80% of differential output; 1200mVpp linear range setting; Fast Input rise/fall time; 27 ps TUSB1002A SLLSF63C – MARCH 2018 – REVISED JULY 2024 www.ti.com 8 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TUSB1002A |
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