TUSB8041RGCT datasheet(15/49 Pages) TI2

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TUSB8041

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SLLSEE4E – JUNE 2014 – REVISED JUNE 2016

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8.3.7 Power-Up and Reset

The TUSB8041 does not have specific power sequencing requirements with respect to the core power (VDD) or

I/O and analog power (VDD33). The core power (VDD) or I/O power (VDD33) may be powered up for an

indefinite period of time while the other is not powered up if all of these constraints are met:

•

All maximum ratings and recommended operating conditions are observed.

•

All warnings about exposure to maximum rated and recommended conditions are observed, particularly

junction temperature. These apply to power transitions as well as normal operation.

•

Bus contention while VDD33 is powered up must be limited to 100 hours over the projected life-time of the

device.

•

Bus contention while VDD33 is powered down may violate the absolute maximum ratings.

A supply bus is powered up when the voltage is within the recommended operating range. It is powered down

when it is below that range, either stable or in transition.

A minimum reset duration of 3 ms is required. This is defined as the time when the power supplies are in the

recommended operating range to the de-assertion of GRSTz. This can be generated using programmable-delay

supervisory device or using an RC circuit.

8.4 Device Functional Modes

8.4.1 External Configuration Interface

The TUSB8041 supports a serial interface for configuration register access. The device may be configured by an

attached I2C EEPROM or accessed as a slave by an SMBus capable host controller. The external interface is

enabled when both the SCL/SMBCLK and SDA/SMBDAT pins are pulled up to 3.3 V at the de-assertion of reset.

The mode, I2C master or SMBus slave, is determined by the state of SMBUSz/SS_SUSPEND pin at reset.

8.4.2 I2C EEPROM Operation

The TUSB8041 supports a single-master, standard mode (100 kbit/s) connection to a dedicated I2C EEPROM

when the I2C interface mode is enabled. In I2C mode, the TUSB8041 reads the contents of the EEPROM at bus

address 1010000b using 7-bit addressing starting at address 0.

If the value of the EEPROM contents at byte 00h equals 55h, the TUSB8041 loads the configuration registers

according to the EEPROM map. If the first byte is not 55h, the TUSB8041 exits the I2C mode and continues

execution with the default values in the configuration registers. The hub will not connect on the upstream port

until the configuration is completed. If the hub detected an un-programmed EEPROM (value other than 55h), the

hub will enter Programming Mode and a Programming Endpoint within the hub will be enabled.

Note, the bytes located above offset Ah are optional. The requirement for data in those addresses is dependent

on the options configured in the Device Configuration, and Device Configuration 2 registers.

For details on I2C operation refer to the UM10204 I2C-bus Specification and User Manual.

8.4.3 SMBus Slave Operation

When the SMBus interface mode is enabled, the TUSB8041 supports read block and write block protocols as a

slave-only SMBus device.

The TUSB8041 slave address is 1000 1xyz, where:

•

x is the state of GANGED/SMBA2/HS_UP pin at reset,

•

y is the state of FULLPWRMGMTz/SMBA1/SS_UP pin at reset, and

•

z is the read/write bit; 1 = read access, 0 = write access.

If the TUSB8041 is addressed by a host using an unsupported protocol it will not respond. The TUSB8041 will

wait indefinitely for configuration by the SMBus host and will not connect on the upstream port until the SMBus

host indicates configuration is complete by clearing the CFG_ACTIVE bit.

For details on SMBus requirements refer to the System Management Bus Specification.

TUSB8041RGCT 数据表(PDF) 15 Page - Texas Instruments

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