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TUSB8041RGCT 数据表(PDF) 34 Page - Texas Instruments |
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TUSB8041RGCT 数据表(HTML) 34 Page - Texas Instruments |
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34 / 49 page  VDD11 VDD33 BOARD_3P3V BOARD_1P1V C36 0.1uF TUSB8041 U1G NC 60 VDD33 34 VDD33 52 VDD33 63 VDD33 16 C26 0.1uF C35 0.1uF C32 0.1uF C30 0.1uF C27 0.1uF C31 0.1uF FB6 220 @ 100MHZ C34 0.1uF C33 10uF C38 10uF C37 0.1uF C29 0.1uF C28 0.1uF FB5 220 @ 100MHZ C39 1uF C41 18pF TUSB8041 U1F GRSTN 50 XO 61 XI 62 SDA/SMBDAT 37 SCL/SMBCLK 38 SMBUSZ/SS_SUSPEND 39 PWRCTL_POL 41 AUTOENZ/HS_SUSPEND 45 TEST 49 USB_R1 64 C40 18pF Y1 24MHz R18 4.7K 0402 5% R14 1M R15 9.53K 0402 1% R16 4.7K 34 TUSB8041 SLLSEE4E – JUNE 2014 – REVISED JUNE 2016 www.ti.com Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated 9.2.1.2.7 Clock, Reset, and Misc The PWRCTL_POL is left unconnected which results in active high power enable (PWRCTL1, PWRCTL2, PWRCTL3, and PWRCTL4) for a USB VBUS power switch. The 1 µF capacitor on the GRSTN pin can only be used if the VDD11 supply is stable before the VDD33 supply. The depending on the supply ramp of the two supplies the capacitor may have to be adjusted. Figure 11. Clock, Reset, and Misc 9.2.1.2.8 TUSB8041 Power Implementation Figure 12. TUSB8041 Power Implementation |
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