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TUSB8041RGCT 数据表(PDF) 28 Page - Texas Instruments |
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TUSB8041RGCT 数据表(HTML) 28 Page - Texas Instruments |
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28 / 49 page  28 TUSB8041 SLLSEE4E – JUNE 2014 – REVISED JUNE 2016 www.ti.com Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated 8.5.23 Device Status and Command Register Table 46. Register Offset F8h Bit No. 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 Table 47. Bit Descriptions – Device Status and Command Register Bit Field Name Access Description 7:2 RSVD RO Reserved. Read only, returns 0 when read. 1 smbusRst RSU SMBus interface reset. This bit loads the registers back to their GRSTz values. This bit is set by writing a 1 and is cleared by hardware on completion of the reset. A write of 0 has no effect. 0 cfgActive RCU Configuration active. This bit indicates that configuration of the TUSB8041 is currently active. The bit is set by hardware when the device enters the I2C or SMBus mode. The TUSB8041 shall not connect on the upstream port while this bit is 1. When in the SMBus mode, this bit must be cleared by the SMBus host in order to exit the configuration mode and allow the upstream port to connect. The bit is cleared by a writing 1. A write of 0 has no effect. |
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