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TUSB8041

SLLSEE4E – JUNE 2014 – REVISED JUNE 2016

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(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report (SPRA953).

(2)

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3)

The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4)

The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5)

The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6)

The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).

(7)

The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

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7.4 Thermal Information

THERMAL METRIC(1)

TUSB8041

UNIT

RGC

64 PINS

RθJA

Junction-to-ambient thermal resistance(2)

26

°C/W

RθJCtop

Junction-to-case (top) thermal resistance(3)

11.5

RθJB

Junction-to-board thermal resistance(4)

5.3

ψJT

Junction-to-top characterization parameter(5)

0.2

ψJB

Junction-to-board characterization parameter(6)

5.2

RθJCbot

Junction-to-case (bottom) thermal resistance(7)

1.0

(1)

Applies to external inputs and bidirectional buffers.

(2)

Applies to external outputs and bidirectional buffers.

(3)

Applies to GRSTz.

(4)

Applies to pins with internal pullups/pulldowns.

(5)

Applies to external input buffers.

7.5 Electrical Characteristics, 3.3-V I/O

over operating free-air temperature range (unless otherwise noted)

PARAMETER

OPERATION

TEST CONDITIONS

MIN

MAX

UNIT

VIH

High-level input voltage(1)

VDD33

2

VDD33

V

VIL

Low-level input voltage(1)

VDD33

0

0.8

V

JTAG pins only

0

0.55

VI

Input voltage

0

VDD33

V

VO

Output voltage(2)

0

VDD33

V

tt

Input transition time (trise and tfall)

0

25

ns

Vhys

Input hysteresis(3)

0.13 x VDD33

V

VOH

High-level output voltage

VDD33

IOH = -4 mA

2.4

V

VOL

Low-level output voltage

VDD33

IOL = 4 mA

0.4

V

IOZ

High-impedance, output current(2)

VDD33

VI = 0 to VDD33

±20

µA

IOZP

High-impedance, output current with

internal pullup or pulldown

resistor(4)

VDD33

VI = 0 to VDD33

±250

µA

II

Input current(5)

VDD33

VI = 0 to VDD33

±15

µA