IMSA110 datasheet(18/26 Pages) STMICROELECTRONICS

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PSRB control

PCRB[10-0]

Default: 0

…

…0

These eleven least significant bits of the PCRB are

used to specify the length of the second Program-

mable Shift Register (PSRB). The length of the shift

loaded in these bits. The value loaded in must be

in the range of 0 to 1120 decimal. If a value outside

this range is written to these bits the behaviour of

the shift register will be undefined. After updating

this register will also have to propagate through

PSRA and the backend before the cascade output

values will be correct

Reserved

PCRB[15-11]

Default: 00000

These 5 most significant bits of the PCRB are

reserved. The user should write zero to these loca-

tions to maintain compatibility with future products.

The value read from these locations will be zero.

PSRC control

PCRC[10-0]

Default: 0

…

…0

These eleven least significant bits of the PCRC are

used to specify the length of the first Programmable

Shift Register (PSRC). The length of the shift reg-

ister will be numerically equal to the binary value

loaded in these bits. The value loaded in must be

in the range of 0 to 1120 decimal. If a value outside

this range is written to these bits the behaviour of

the shift register will be undefined. After updating

this register will also have to propagate through

PSRB, PSRA and the backend before the cascade

output values will be correct

Reserved

PCRC[15-11]

Default: 00000

These 5 most significant bits of the PCRC are

reserved. The user should write zero to these loca-

tions to maintain compatibility with future products.

The value read from these locations will be zero.

10.2 Static control register (SCR)

Reserved

SCR[7]

Default: 0

This location is reserved. The user should write

zero to this location to maintain compatibility with

future products. The value read from this location

will be zero.

Positive Look up

table address

SCR[6]

Default: 0

This bit affects the way in which the over/under

select detector checks the LUT address. It deter-

mines whether the address range of the LUT is

signed (-128 to 127) or positive (0 to 255). A one at

this location indicates a positive LUT address.

PSR out Enable

SCR[5]

Default: 0

A zero at this location will force the PSR Output pins

into the tristate mode.

Cascade Enable

SCR[4]

Default: 0

A zero at this location will force the Cascade Output

pins into the tristate mode.

Unsigned coefficient

load

SCR[3]

Default: 0

If this bit is set to one, the format of subsequently

loaded coefficients become unsigned, with coeffi-

cient value assuming a range between 0 and 255

decimal. An 8-bit coefficient with all its bits set to

one will represent +255 decimal. When this bit is

zero the format of subsequently loaded coefficients

will be twos complement and the corresponding

numerical value will have a range between -128

and +127. By changing this bit whilst coefficients

are being loaded, coefficients between -128 and

+255 can be used. The unsigned format on all

coefficients is suitable when IMS A110s are com-

bined to obtain wider coefficients for extended pre-

cision.

SCR[3]

Coefficient type

Signed coefficients *

Unsigned coefficients

Unsigned data

SCR[2]

Default: 0

If this bit is set to one, the IMS A110 input data

format will become unsigned, with input data value

assuming a range between 0 and 255 decimal. An

8-bit value with all its bits set to one will represent

+255 decimal. When this bit is zero the input data

format will be twos complement and the corre-

sponding numerical value will have a range be-

tween -128 and +127. Unlike SCR[3], this bit cannot

be used to dynamically alter the data format. The

unsigned format is suitable when IMS A110s are

combined to obtain wider input data for extended

precision.

SCR[2]

Data type

Signed data *

Unsigned data

Bypass shift registers SCR[1]

Default: 0

This bit is used to program the path between the

PSRin and PSRout ports. A zero at this location will

cause the output from the last programmable shift

this bit will cause the three programmable shift

registers to be bypassed, and the data entering the

port PSRin to be fed directly, via a delay of 2 clock

cycles, to the port PSRout. This bit allows full pro-

grammability of a cascade arrangement so that the

same hardware can be operated in a variety of

ways.

IMSA110

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