FT201XS-R datasheet(14/49 Pages) FTDI

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FT201X USB I2C SLAVE IC Datasheet

Version 1.4

Document No.: FT_000627 Clearance No.: FTDI# 264

input receiver and two single ended input receivers provide USB data in, Single-Ended-0 (SE0) and USB

reset detection conditions respectfully. This function also incorporates a 1.5kΩ pull up resistor on USBDP.

The block also detects when connected to a USB power supply which will not enumerate the device but

still supply power and may be used for battery charging.

USB DPLL. The USB DPLL cell locks on to the incoming NRZI USB data and generates recovered clock

and data signals for the Serial Interface Engine (SIE) block.

Internal 12MHz Oscillator - The Internal 12MHz Oscillator cell generates a 12MHz reference clock. This

provides an input to the x4 Clock Multiplier function. The 12MHz Oscillator is also used as the reference

clock for the SIE, USB Protocol Engine and UART FIFO controller blocks.

Clock Multiplier / Divider. The Clock Multiplier / Divider takes the 12MHz input from the Internal

Oscillator function and generates the 48MHz, 24MHz, 12MHz and 6MHz reference clock signals. The 48Mz

clock reference is used by the USB DPLL and the Baud Rate Generator blocks.

Serial Interface Engine (SIE). The Serial Interface Engine (SIE) block performs the parallel to serial

and serial to parallel conversion of the USB data. In accordance with the USB 2.0 specification, it

performs bit stuffing/un-stuffing and CRC5/CRC16 generation. It also checks the CRC on the USB data

stream.

USB Protocol Engine. The USB Protocol Engine manages the data stream from the device USB control

endpoint. It handles the low level USB protocol requests generated by the USB host controller and the

commands for controlling the functional parameters of the I2C in accordance with the USB 2.0

specification chapter 9.

FIFO RX Buffer (512 bytes). Data sent from the USB host controller to the I2C interface via the USB

data OUT endpoint is stored in the FIFO RX (receive) buffer. Data is removed from the buffer to the I2C

transmit register under control of the I2C Controller. (Rx relative to the USB interface).

FIFO TX Buffer (512 bytes). Data from the I2C receive register is stored in the TX buffer. The USB host

controller removes data from the FIFO TX Buffer by sending a USB request for data from the device data

IN endpoint. (Tx relative to the USB interface).

I2C Controller. Module to handle the latching in and out of serial data on the I2C interface. Supports up

to 3.4MHz, High Speed Serial Mode.

RESET Generator - The integrated Reset Generator Cell provides a reliable power-on reset to the device

internal circuitry at power up. The RESET# input pin allows an external device to reset the FT201X.

RESET# can be tied to 3V3OUT.

FT201XS-R 数据表(PDF) 14 Page - Future Technology Devices International Ltd.