Data Sheet

ADGM3121

SPECIFICATIONS

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Rev. 0 | 8 of 33

TIMING CHARACTERISTICS

VDD = 3.0V to 3.6V, GND = 0V and all specifications TMIN to TMAX, unless otherwise noted.

Table 2. Timing Characteristics

Parameter

Limit at TMIN

Limit at TMAX

Unit

Conditions

t1

100

ns

SCLK period

t2

45

ns

SCLK high pulse width

t3

45

ns

SCLK low pulse width

t4

25

ns

CS falling edge to SCLK active edge

t5

20

ns

Data setup time

t6

20

ns

Data hold time

t7

25

ns

SCLK active edge to CS rising edge

t8

20

ns

CS falling edge to SDO data available

t91

40

ns

SCLK falling edge to SDO data available

t10

25

ns

CS rising edge to SDO data available

t11

100

ns

CS high time between SPI commands

t12

25

ns

SCLK edge rejection to CS falling edge

t13

25

ns

CS rising edge to SCLK edge rejection

1 Measured with a 20pF load. t9 determines the maximum SCLK frequency when SDO is used.

Timing Diagrams

Figure 2. Addressable Mode Timing