LTC6754

6

6754f

For more information www.linear.com/LTC6754

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

tJIT_RMS

RMS Jitter, Sine Wave Input

VIN=200mVP–P

fIN=245.76MHz, Jitter BW=10Hz–122.88MHz

fIN=245.76MHz, Jitter BW=12kHz–20MHz

fIN=100MHz, Jitter BW=10Hz–50MHz

fIN=100MHz, Jitter BW=12kHz–20MHz

fIN=61.44MHz, Jitter BW=10Hz–30.72MHz

fIN=61.44MHz, Jitter BW=12kHz–20MHz

fIN=10MHz, Jitter BW=10Hz–5MHz

1.6

0.73

2.2

1.36

3

2.4

19

ps

ps

ps

ps

ps

ps

ps

Latching/Adjustable Hysteresis Characteristics

VLE/HYST

LE/HYST Pin Voltage

Open Circuit

l

1.05

1.25

1.45

V

RHYST

Resistor Value at LE/HYST

LE/HYST Pin Voltage < Open Circuit Value

l

11.6

14.5

17.6

kΩ

VHYST_LARGE Hysteresis Voltage

VLE/HYST = 800mV

43

mV

VIL_LE

Latch Pin Voltage, Latch Guaranteed

l

0.4

V

VIH_LE

Latch Pin Voltage, Hysteresis Disabled

l

1.7

V

IIH_LE

Latch Pin Current High

VLE/HYST = 1.7V

l

31

70

µA

IIL_LE

Latch Pin Current Low

VLE/HYST = 0.4V

l

–78

–58

µA

tSETUP

Latch Setup Time

2

ns

tHOLD

Latch Hold Time

–2

ns

tPL

Latch to Output Delay

3

ns

Shutdown Characteristics

ISD_VCCI

Shutdown Mode Input Stage Supply Current

VSHDN = 0.8V

l

650

880

970

μA

µA

ISD_VCCO

Shutdown Mode Output Stage Supply Current

VSHDN = 0.8V

l

240

370

380

μA

µA

ISD_TOT

Shutdown Mode Total Supply Current

VSHDN = 0.8V

l

0.89

1.25

1.35

mA

mA

tSD

Shutdown Time

Output Hi-Z

110

ns

VIH_SD

Shutdown Pin Voltage High

Part Guaranteed to be Powered On

l

2

V

VIL_SD

Shutdown Pin Voltage Low

Part Guaranteed to be Powered Off

0.8

V

tWAKEUP

Wake-Up Time from Shutdown

VOVERDRIVE = 100mV, Output Valid

120

ns

The l denotes the specifications which apply

over the specified temperature range, otherwise specifications are at TA = 25°C, LE/HYST, SHDN pins floating, VOVERDRIVE = 50mV,

–IN = VCM = 300mV, +IN = –IN + VOVERDRIVE, 150mV step size, RL=100Ω , unless otherwise noted.

elecTrical characTerisTics (VCCI = VCCO = 2.5V)

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: Reverse biased ESD protection exists on all input, shutdown,

latching/hysteresis and output pins. If the voltage on the input, shutdown,

or latching/hysteresis pins goes beyond either input supply, the current

should be limited to less than 10mA. This parameter is guaranteed to meet

specification through design and/or characterization. It is not production

tested.

Note 3: A heat sink may be required to keep the junction temperature

below the absolute maximum rating. This parameter is guaranteed to meet

specified performance through design and/or characterization. It is not

production tested.

Note 4: The LTC6754I is functional and guaranteed to meet specified

performance from –40 °C to 85 °C. The LTC6754H is functional and

guaranteed to meet specified performance from –40 °C to 125 °C.

Note 5: Supply voltage range is guaranteed by the PSRR test.

Note 6: Both hysteresis and offset are measured by determining positive

and negative trip points (input values needed to change the output in the

opposite direction). Hysteresis is defined as the difference of the two trip

points and offset as the average of the two trip points.

Note 7: Guaranteed by CMRR spec.

Note 8: Propagation delays are measured with a step size of 150mV.

Note 9: Latch setup time is defined as the minimum time before the

LE/HYST pin is asserted low for an input signal change to be acquired and

held at the output. Latch hold time is defined as the minimum time before

an input signal change for a high to low transition on the LE/HYST pin to

prevent the output from changing. Latch enable pulse width is defined as

the minimum time for the LE/HYST pin to be held high for an input change

to affect the output. See Figure 7 for a graphical definition of these terms.

Note 10: The devices have effectively infinite gain when hysteresis is

enabled.