LTC6754

16

6754f

For more information www.linear.com/LTC6754

Typical applicaTions

High Speed Clock Recovery and Level Translation

Circuit

High speed comparators are often used in digital systems

torecoverdistortedclockwaveforms.TheLTC6754canbe

used to recover a distorted TTL clock signal, and translate

it into a signal suitable for driving an LVDS receiver.

In this application, an input clock signal is required to drive

an LVDS receiver. If the input signal gets distorted and

its amplitude severely reduced due to stray capacitance,

stray inductance or due to reflections on the transmission

line, the LTC6754 can be used to convert it into a full scale

LVDS signal that can drive the receiver.

Figure  10 shows the input and output waveforms of

the LTC6754, used to recover a 400mVP–P 340MHz

(680Mbps) corrupted clock signal, into a full scale LVDS

output signal. AC-coupling could have been used at the

input of the comparator, however to preserve input duty

cycle information DC-coupling may be preferable, and

that is where having a wide input common mode range

is an advantage. The input to output delay on the graph

is larger than the actual propagation delay. The additional

delay is due to the measurement cables.

VCCI V

CCO

VEE + 3.3V

6754 F09

340MHz

CLOCK INPUT

VEE

VREF = 200mV

LTC6754

100

–

+

Q

Q

LTC6754

Figure 9. Corrupted Clock Recovery to LVDS Translator Circuit.

1ns/DIV

INPUT

200mV/DIV

0V

Q OUTPUT

Q OUTPUT

100mV/DIV

VOCM = 1.25V

6754 F10

Figure 10. LVDS Output at 340MHz

in parallel with multiple low ESL, low ESR 100nF capaci-

tors connected as close to the supply pins as possible

to minimize trace impedance is recommended. In many

applications the VEE pin will be connected to ground. In

applications where the VEE pin is not connected to ground,

the positive supplies should still be bypassed to VEE. The

VEE pin should also then be bypassed to a ground plane

with a 2.2μF capacitor in parallel with low ESL, low ESR

100nF capacitors if possible.

Fordeviceswithseparatepositiveinputandoutputsupplies,

bypass capacitors should be placed from each positive

supply to VEE. Capacitors should NOT be placed between

the two positive supplies; otherwise disturbances due to

output switching can couple back to the inputs.

When the input slew rate is small, sustained oscillations

can occur at the output pin while the input is transitioning

due to even one millivolt of ground bounce. For applica-

tions where the input slew rate is low, internal hysteresis

should not be removed by taking the LE/HYST pin high,

as the addition of hysteresis makes the comparators more

immune to disturbances such as ground bounce. Increas-

ing hysteresis by adjusting the LE/HYST pin voltage or by

adding positive feedback as discussed in the section on

hysteresiscanfurtherimprovenoiseimmunity.Whenadd-

ing positive feedback, surface mounted resistors should

be used for R1 and R2 in Figure 6. The resistors should

be as close to the device as possible.

applicaTions inForMaTion