LTC6754

11

6754f

For more information www.linear.com/LTC6754

Circuit Description

The block diagram of the LTC6754 is shown in Figure 1.

There are differential inputs (+IN, –IN), a negative power

supply (VEE), two positive supply pins: VCCI for the input

stageandVCCOfortheoutputstage,twooutputpins(Qand

Q), a pin for latching and adjusting hysteresis (LE/HYST),

and a pin to put the device in a low power mode (SHDN).

The signal path consists of a rail-to-rail input stage, an

intermediate gain stage and an output driver stage to an

output stage that sources or sinks 3.6mA between the two

output pins, depending on the polarity of the differential

input (+IN – –IN). The output stage also has a common

mode feedback network that keeps the average of Q and

Q approximately 1.26V. A Latching/Hysteresis interface

block allows the user to latch the output state and/or

remove or adjust the comparator input hysteresis. All of

the internal signal paths make use of low voltage swings

for high speed at low power.

Power Supply Configurations

The LTC6754UD (QFN Package) has separate positive

supply pins for the input and output stages that allow for

better isolation between the sensitive inputs and circuitry

connected to the output load by removing a direct path for

noise coupling through the positive supply. This feature

also allows the user the ability to decouple input signal

range from output stage power consumption (for example

by using a 5.25V input supply to allow for > 5V common

mode input range and a 2.4V output supply to minimize

total power consumption). Figure 2 shows a few possible

configurations.

For proper and reliable operation both supply pins should

be between 2.4V and 5.25V above the negative supply pin.

applicaTions inForMaTion

There are no restrictions regarding the sequence in which

the positive or negative supplies are applied as long as the

absolute maximum ratings are not violated.

Input Voltage Range and Offset

The LTC6754 family uses a rail-to-rail input stage that

consists of a PNP pair and an NPN pair that are active

over different input common mode ranges. The PNP pair

is active for inputs between VEE – 0.2V and approximately

VCCI – 1.5V (low common mode region of operation).

The NPN pair is active for inputs between approximately

VCCI – 1V and VCCI + 0.1V (high common mode region of

operation). Partial activation of both pairs occurs when

one input is in the low common mode region of operation

and the other input is in the high common mode region

of operation, or either of the inputs is between approxi-

mately VCCI – 1.5V and VCCI – 1V (transition region). The

device has small, trimmed offsets as long as both inputs

are completely in the low or high common mode region

of operation. In the transition region, the offset voltage

may increase. Applications that require good DC precision

should avoid the transition region.

Input Bias Current

When both inputs are in the low common mode region,

the input bias current is negative, with current flowing

out of the input pins. When both inputs are in the high

common mode region, the input bias current is positive,

with current flowing into the input pins. The input stage

hasbeendesignedtoaccommodatelargedifferentialinput

voltageswithoutlargeincreasesininputbiascurrent.With

one input at the positive input supply rail and the other

input at the negative supply rail, the magnitude of the

input bias current at either pin is typically less than 3.5μA.

VCCI

Q

100

Q

–

+

VCCO

5V

3.3V

VEE

0V

–IN

+IN

VCCI

Q

100

Q

–

+

VCCO

2.4V

5V

VEE

0V

–IN

+IN

VCCI

Q

100

Q

–

+

VCCO

3V

3V

VEE

0V

–IN

+IN

6754 F02

(a) SINGLE SUPPLY

(b) OUTPUT SUPPLY < INPUT SUPPLY

(c) OUTPUT SUPPLY > INPUT SUPPLY

Figure 2. Typical Power Supply Configurations Applicable to the LTC6754UD (QFN Package)