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LTC6754ISC6#TRMPBF 数据表(PDF) 14 Page - Analog Devices

部件名 LTC6754ISC6#TRMPBF
功能描述  High Speed Rail-to-Rail Input Comparator with LVDS Compatible Outputs
PDF  22 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

LTC6754ISC6#TRMPBF 数据表(HTML) 14 Page - Analog Devices

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LTC6754
14
6754f
For more information www.linear.com/LTC6754
applicaTions inForMaTion
Latching
TheinternallatchoftheLTC6754UD(QFNpackage)retains
the output state when the LE/HYST pin is taken to less
than 400mV above the negative supply.
Figures 7a to 7e illustrate the latch timing definitions. The
latch setup time is defined as the time for which the input
should be stable before the latch pin is asserted low to
ensure that the correct state will be held at the output. The
latch hold time is the interval after which the latch pin is
asserted in which the input signal must remain stable for
the output to be the correct state at the time latch was
asserted. The latch propagation delay (tPL) is the time
taken for the output to return to input control after the
latch pin is released. Latching is disabled if the LE/HYST
pin is left floating.
6754 F07a
+IN – –IN
t > tSETUP
tPD
Q – Q
LE/HYST
Figure 7a. Input State Change Properly Latched
6754 F07b
+IN – –IN
t < tSETUP
Q – Q
LE/HYST
Figure 7b. Input State Change Setup Time Too Short
6754 F07c
+IN – –IN
t < tHOLD
tPD
Q – Q
LE/HYST
Figure 7c. Input State Not Held Long Enough,
Wrong Output State Latched
6754 F07d
+IN – –IN
t > tHOLD
tPD
Q – Q
LE/HYST
t > tSETUP
Figure 7d. Short Input Pulse Properly Captured and Latched
6754 F07e
+IN – –IN
tPL
Q – Q
LE/HYST
Figure 7e. Latched Output Disabled



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