MPC7441 datasheet(16/60 Pages) FREESCALE

16 / 60 page

MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4

Freescale Semiconductor

Electrical and Thermal Characteristics

Notes:

1. Caution: The SYSCLK frequency and PLL_CFG[0:5] settings must be chosen such that the resulting SYSCLK (bus)

frequency, processor core frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum

operating frequencies. Refer to the PLL_CFG[0:5] signal description in Section 9.1.1, “PLL Configuration,” for valid

PLL_CFG[0:5] settings.

2. Actual maximum system bus frequency is system-dependent. See Section 5.2.1, “Clock AC Specifications.”

3. Rise and fall times for the SYSCLK input measured from 0.4 to 1.4 V

4. Timing is guaranteed by design and characterization.

5. Guaranteed by design

6. The SYSCLK driver’s closed loop jitter bandwidth should be less than 1.5 MHz at –3 dB.

7. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for PLL

lock after a stable VDD and SYSCLK are reached during the power-on reset sequence. This specification also applies when

the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted

for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.

8. This reflects the maximum and minimum core frequencies when the dynamic frequency switching feature (DFS) is disabled.

fcore_DFS provides the maximum and minimum core frequencies when operating in a DFS mode.

9.This specification supports the Dynamic Frequency Switching (DFS) feature and is applicable only when one of the DFS modes

(divide-by-2 or divide-by-4) is enabled. When DFS is disabled, the core frequency must conform to the maximum and minimum

frequencies stated for fcore.

10.Use of the DFS feature does not affect VCO frequency.

Table 8. Clock AC Timing Specifications

At recommended operating conditions. See Table 4.

Characteristic

Symbol

Maximum Processor Core Frequency (Speed Grade)

Unit

Notes

1000 MHz

1420 MHz

1600 MHz

1700 MHz

Min

Max

Min

Max

Min

Max

Min

Max

Processor

core

frequency

DFS mode disabled

fcore

600

1000

600

1420

600

1600

600

1700

MHz

1, 8

DFS mode enabled

fcore_DF

300

500

300

710

300

800

300

850

VCO frequency

fVCO

600

1000

600

1420

600

800

600

1700

MHz

1, 10

SYSCLK frequency

fSYSCLK

200

MHz

1, 2, 8

SYSCLK cycle time

tSYSCLK

5.0

SYSCLK rise and fall time

tKR, tKF

—0.5

SYSCLK duty cycle measured at

OVDD/2

tKHKL/

tSYSCLK

SYSCLK cycle-to-cycle jitter

—

150

—

150

—

150

—

150

5, 6

Internal PLL relock time

—

100

—

100

—

100

—

100

μs7

MPC7441 数据表(PDF) 16 Page - Freescale Semiconductor, Inc

MPC7441 数据表(HTML) 16 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

数据表下载