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MPF0900AMMA2ES 数据表(PDF) 101 Page - NXP Semiconductors |
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MPF0900AMMA2ES 数据表(HTML) 101 Page - NXP Semiconductors |
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101 / 205 page  NXP Semiconductors PF09 Nine-channel power management IC with advanced system safety monitoring [2] Typical high-side FET resistance due to packaging (bondwire + metal) at room temperature is 20.5mΩ. [3] Typical low-side FET resistance due to packaging (bondwire + metal) at room temperature is 21mΩ. Symbol Description Min Typ Max Units L Output inductor • Typical inductor DC resistance: < 25 mΩ • Minimum saturation current at full load: 7.0 A – 0.47 – µH COUT Effective output capacitance • 2x22 μF, 6.3 V • Low equivalent series resistance (ESR) ceramic capacitor 22 44 300 µF CIN Input capacitor • 4.7 μF, 10 V • Low ESR ceramic capacitor 4.23 4.7 5.17 µF Table 125. Recommended external components. 13.2.3 SW2 - SW5 (2.5 A peak/valley current mode buck regulator) The PF09 features four low-voltage, multiphase, peak current mode (PCM) or valley current mode (VCM) buck regulators with wide output voltage ranges from 0.3 V to 3.3 V, with up to 1.5 % output accuracy and 2.5 A nominal load current capability. The default voltage configuration for the SWx regulator at power-up is set in OTP via the OTP_VSWx_RUN[7:0] bits, and the dynamic configuration of the output voltage during the RUN state is controlled via the VSWx_RUN[7:0] functional bits. The default voltage configuration for the SWx regulator to be used during the STANDBY state is set in OTP via the OTP_VSWx_STBY[7:0] bits, and the MCU can modify the target STANDBY voltage configuration of the SWx regulator during any of the SYSTEM ON states via the VSWx_STBY[7:0] functional bits. The MCU is expected to update the VSWx_STBY[7:0] bits before directing the PMIC to enter the STANDBY state. The selection of the VSWx_STBY[7:0] bits will depend on the system requirements of the specific low- power mode it wants to achieve at system level. VSWx_RUN[7:0] VSWx_STBY[7:0] Voltage setting 0x00 0.30000V 0x01 to 0x91 0.45000 V to 1.35000 V in 6.25 mV steps 0x92 to 0x9E Reserved 0x9F 1.50000 V 0xA0 to 0xD8 1.80000 V to 2.50000 V in 12.5 mV steps 0xD9 to 0xDF Reserved 0xE0 to 0xF4 2.80000 V to 3.30000 V in 25.0 mV steps 0xF5 to 0xFF Reserved Table 126. SW2 voltage setting DVS is available under the following conditions: 1. DVS range is between 0.65 V and 0.9 V. 2. The OV/UV threshold is +/-5 % or wider. 3. The DVS ramp must be 3.9 mV/μs or slower. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 1.3 — 16 December 2025 Document feedback 101 / 205 |
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