MPF0900AMMA2ES datasheet(117/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

OTP_VLDOxMON_TSET[1:0]

VLDOxMON blanking time

250 µs

500 µs

1000 µs

2500 µs

Table 152. VLDOxMON blanking time configuration bits

The default blanking time is set in the OTP registers, and it is available only during the LDOx turn-on transition

in the Power-up or RUN state, where the LDOx block is operating as a voltage monitor for an external supply.

If the external supply reaches point of regulation before the settling timer has expired, the VLDOxMON will start

monitoring right away, even before the blanking timer has ended. Refer to section LDO2 / LDO3 External VMON

Operation for a detailed description of the VMON operation on the LDOx block.

If the VLDOxMON voltage selection is changed from one set point to another during the RUN state, the

VLDOxMON will use the VLDOxMON_TMASK[1:0] bits to defined the masking timer for the OV and UV fault

monitoring while the output voltage transitions to the new expected level.

VLDOxMON_TMASK[3:0]

VLDOxMON masking timer

500 µs

1000 µs

2000 µs

5000 µs

Table 153. VLDOxMON masking timer

When the PF09 transitions to the STANDBY state, the LDOx will use the LDOx_STBY_EN bit to decide whether

or not to enable the LDOx output to support the low-power operation. If the LDOx_STBY_EN = 1, then the

LDOx output will be turned on in the corresponding time slot as set by the VLODx_SEQ[7:0] bits.

When the device goes into the STANDBY state, the operation of the internal voltage monitor (VLDOxMON) will

depend on whether the PF09 is in the monitored STANDBY or the low power STANDBY states.

Monitored STANDBY mode (OTP_LP_STBY = 0): in this mode, the LDO output will be monitored internally.

During the transition into the Monitored STANDBY state, if the LDOx target voltage in the STANDBY state is

lower than the RUN state voltage, the PF09 will apply an internal discharge resistor during the transition to

ensure the LDO output is discharged properly and no false OV/UV condition is flagged.

Note: Because the bypass mode of operation is intended to achieve very low power consumption in the power

architecture, it is not recommended to use the Bypass mode when the system is prioritizing system monitoring

over current consumption during the STANDBY mode.

Low-power STANDBY mode (OTP_LP_STBY = 1): in this mode, no voltage monitoring is available and the

internal VLDOxMON will be disabled. During the transition to the low-power STANDBY state, the LDOx output

will remain tri-stated. Voltage discharge will be performed by the external load, to maximize power utilization in

the Low-power mode.

When using the LDOx Bypass mode, it is responsibility of the system integrator to ensure the external voltage

regulator is properly disabled in the correct sequence and is able to disable its output with high impedance,

in order to allow a seamless transition between the external supply and the LDOx supplying the MCU core

domain.

Likewise, the external voltage regulator must support pre-bias turn on conditions to allow proper transition

between the voltage regulators.

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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