STM32L4P5CE datasheet(45/311 Pages) STMICROELECTRONICS

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DS12903 Rev 2

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STM32L4P5xx

Functional overview

LCD parallel interface

The FMC can be configured to interface seamlessly with most graphic LCD controllers. It

supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to

specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost

effective graphic applications using LCD modules with embedded controllers or high-

performance solutions using external controllers with dedicated acceleration.

3.19

Octo-SPI interface (OCTOSPI)

The OCTOSPI is a specialized communication interface targetting single, dual, quad or octal

SPI memories. It can operate in any of the three following modes:

•

Indirect mode: all the operations are performed using the OCTOSPI registers

•

Status polling mode: the external memory status register is periodically read and an

interrupt can be generated in case of flag setting

•

Memory-mapped mode: the external memory is memory mapped and is seen by the

system as if it were an internal memory supporting read and write operation

The OCTOSPI supports two frame formats:

•

Classical frame format with command, address, alternate byte, dummy cycles and data

phase over 1, 2, 4 or 8 data pins

•

HyperbusTM frame format

The OCTOSPI offers the following features:

•

Three functional modes: indirect, status-polling, and memory-mapped

•

Read and write support in memory-mapped mode

•

Supports for single, dual, quad and octal communication

•

Dual-quad mode, where 8 bits can be sent/received simultaneously by accessing two

quad memories in parallel.

•

SDR and DTR support

•

Data strobe support

•

Fully programmable opcode for both indirect and memory mapped mode

•

Fully programmable frame format for both indirect and memory mapped mode

•

Each of the five following phases can be configured independently (enable, length,

single/dual/quad communication)

–

Instruction phase

–

Address phase

–

Alternate bytes phase

–

Dummy cycles phase

–

Data phase

•

HyperbusTM support

•

Integrated FIFO for reception and transmission

•

8, 16, and 32-bit data accesses are allowed

•

DMA channel for indirect mode operations

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