STM32L4P5CE datasheet(34/311 Pages) STMICROELECTRONICS

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Functional overview

STM32L4P5xx

34/311

DS12903 Rev 2

Low-power timer 2

(LPTIM2)

OOO

O-

Independent

watchdog (IWDG)

OOO

O-

Window watchdog

(WWDG)

OOO

SysTick timer

Touch sensing

controller (TSC)

OOO

Random number

generator (RNG)

O(8)

HASH hardware

accelerator

OOO

CRC calculation

unit

OOO

GPIOs

OOO

(9)

pins

(10)

(11)

pins

(10)

1. Legend: Y = yes (enable). O = optional (disable by default, can be enabled by software). - = not available.

Gray cells highlight the wakeup capability in each mode.

2. The Flash can be configured in power-down mode. By default, it is not in power-down mode.

3. The SRAM clock can be gated on or off. In Stop 2 mode, the content of SRAM3 is preserved or not depending on the

RRSTP bit in PWR_CR1 register.

4. The upper 4 Kbytes or the full SRAM2 content is preserved depending on RRS[1:0] bits configuration in PWR_CR3

5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by

the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not

need it anymore.

6. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or

received frame event.

7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.

8. Voltage scaling range 1 only.

9. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.

10. The I/Os with wakeup from standby/shutdown capability are: PA0, PC13, PE6, PA2, PC5.

11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when

exiting the Shutdown mode.

Table 5. Functionalities depending on the working mode(1) (continued)

Peripheral

Run

Sleep

Low-

power

run

Low-

power

sleep

Stop 0/1

Stop 2

Standby Shutdown

VBAT

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