STM32L4P5CE datasheet(40/311 Pages) STMICROELECTRONICS

40 / 311 page

Functional overview

STM32L4P5xx

40/311

DS12903 Rev 2

3.10

Clock recovery system (CRS)

The devices embed a special block which allows automatic trimming of the internal 48 MHz

oscillator to guarantee its optimal accuracy over the whole device operational range. This

automatic trimming is based on the external synchronization signal, which can be either

derived from USB SOF signalization, from LSE oscillator, from an external signal on

CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also

possible to combine automatic trimming with manual trimming action.

3.11

General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be

achieved thanks to their mapping on the AHB2 bus.

The I/Os alternate function configuration can be locked if needed following a specific

sequence in order to avoid spurious writing to the I/Os registers.

3.12

Multi-AHB bus matrix

The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, DMA2D,

SDMMC1, SDMMC2 and LCD-TFT) and the slaves (Flash memory, RAM, FSMC,

OCTOSPI, AHB and APB peripherals). It also ensures a seamless and efficient operation

even when several high-speed peripherals work simultaneously.

STM32L4P5CE 数据表(PDF) 40 Page - STMicroelectronics