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STM32L4P5CE 数据表(PDF) 50 Page - STMicroelectronics

部件名 STM32L4P5CE
功能描述  Ultra-low-power Arm® Cortex®-M4 32-bit MCUFPU, 150 DMIPS, up to 1-MB Flash memory, 320-KB SRAM, LCD-TFT, ext. SMPS
PDF  311 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STM32L4P5CE 数据表(HTML) 50 Page - STMicroelectronics

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Functional overview
STM32L4P5xx
50/311
DS12903 Rev 2
3.25
Operational amplifier (OPAMP)
The devices embed two operational amplifiers with external or internal follower routing and
PGA capability.
The operational amplifier features:
•
Low input bias current
•
Low offset voltage
•
Low-power mode
•
Rail-to-rail input
3.26
Digital filter for sigma-delta modulators (DFSDM)
The STM32L4P5xx devices embed one DFSDM with two digital filters modules and four
external input serial channels (transceivers) or alternately four internal parallel inputs
support.
The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to the
microcontroller and then to perform digital filtering of the received data streams (which
represent analog value on Σ∆ modulators inputs).
The DFSDM can also interface the PDM (pulse density modulation) microphones and
perform PDM to PCM conversion and filtering in hardware. The DFSDM features optional
parallel data stream inputs from microcontrollers memory (through DMA/CPU transfers into
DFSDM).
The DFSDM transceivers support several serial interface formats (to support various Σ∆
modulators) and the DFSDM digital filter modules perform digital processing according to
the user’s selected filter parameters with up to 24-bit final ADC resolution.
The DFSDM peripheral supports:
•
4 multiplexed input digital serial channels:
–
Configurable SPI interface to connect various SD modulator(s)
–
Configurable Manchester coded 1 wire interface support
–
PDM (pulse density modulation) microphone input support
–
Maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)
–
Clock output for SD modulator(s): 0..20 MHz
•
Alternative inputs from 8 internal digital parallel channels (up to 16-bit input resolution):
–
Internal sources: device memory data streams (DMA)
•
2 digital filter modules with adjustable digital signal processing:
–Sincx filter: filter order/type (1..5), oversampling ratio (up to 1..1024)
–
Integrator: oversampling ratio (1..256)
•
Up to 24-bit output data resolution, signed output data format
•
Automatic data offset correction (offset stored in register by user)
•
Continuous or single conversion
•
Start-of-conversion triggered by:
–
Software trigger
–
Internal timers



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