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STM32L4P5CE 数据表(PDF) 161 Page - STMicroelectronics |
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STM32L4P5CE 数据表(HTML) 161 Page - STMicroelectronics |
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161 / 311 page ![]() Table 40. Typical consumption in Run and Low-power run modes, with different codes running from SRAM1 and power supplied by external SMPS Symbol Parameter Conditions(1) TYP Unit TYP Unit - VDD12 fHCLK Code 25°C 25°C IDD (Run) Supply current in Run mode fHCLK=fHSE up to 48 MHZ included, bypass mode PLL ON above 48 MHz all peripherals disable VDD12=1.00 V fHCLK= 26 MHz Reduced code 1.13 mA 43 µA/MHz Coremark 1.13 43 Dhrystone2.1 1.13 43 Fibonacci 1.11 43 While(1) 1.07 41 VDD12=1.10V fHCLK= 26 MHz Reduced code 1.36 mA 52 µA/MHz Coremark 1.36 52 Dhrystone2.1 1.36 52 Fibonacci 1.34 52 While(1) 1.29 50 fHCLK= 80 MHz Reduced code 3.77 mA 47 µA/MHz Coremark 3.56 44 Dhrystone2.1 3.77 47 Fibonacci 3.77 47 While(1) 3.77 47 VDD12=1.20V fHCLK= 120 MHz Reduced code 6.82 mA 57 µA/MHz Coremark 6.22 52 Dhrystone2.1 6.82 57 Fibonacci 6.62 55 While(1) 6.62 55 1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%. |
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