STM32L4P5CE datasheet(221/311 Pages) STMICROELECTRONICS

221 / 311 page

DS12903 Rev 2

221/311

STM32L4P5xx

Electrical characteristics

277

Figure 39. ADC accuracy characteristics

Figure 40. Typical connection diagram using the ADC

1. Refer to Table 77: ADC characteristics for the values of RAIN and CADC.

2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

pad capacitance (refer to Table 71: I/O static characteristics for the value of the pad capacitance). A high

Cparasitic value downgrades the conversion accuracy. To remedy this, fADC should be reduced.

3. Refer to Table 71: I/O static characteristics for the values of Ilkg.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 26: STM32L4P5xx

power supply scheme. The 10 nF capacitor should be ceramic (good quality) and it should

be placed as close as possible to the chip.

ET = total unajusted error: maximum deviation

between the actual and ideal transfer curves.

EO = offset error: maximum deviation

between the first actual transition and

the first ideal one.

EG = gain error: deviation between the last

ideal transition and the last actual one.

ED = differential linearity error: maximum

deviation between actual steps and the ideal ones.

EL = integral linearity error: maximum deviation

between any actual transition and the end point

correlation line.

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(3) End point correlation line

4095

4094

4093

4093 4094 4095 4096

VDDA

VSSA

1 LSB IDEAL

(1)

(3)

(2)

MS19880V2

MS33900V5

Sample and hold ADC converter

12-bit

converter

Cparasitic

(2)

Ilkg

(3)

CADC

VDDA

RAIN

(1)

VAIN

AINx

RADC

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