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STM32L4P5CE 数据表(PDF) 235 Page - STMicroelectronics |
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STM32L4P5CE 数据表(HTML) 235 Page - STMicroelectronics |
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235 / 311 page ![]() DS12903 Rev 2 235/311 STM32L4P5xx Electrical characteristics 277 6.3.25 DFSDM characteristics Unless otherwise specified, the parameters given in Table 91 for DFSDM are derived from tests performed under the ambient temperature, fAPB2 frequency and VDD supply voltage conditions summarized in Table 21: General operating conditions. • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 x VDD Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (DFSDM1_CKINy, DFSDM1_DATINy, DFSDM1_CKOUT for DFSDM). Table 91. DFSDM characteristics(1) Symbol Parameter Conditions Min Typ Max Unit fDFSDMCLK DFSDM clock 1.71 < VDD < 3.6 V - - fSYSCLK MHz fCKIN (1/TCKIN) Input clock frequency SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 1.71 < VDD < 3.6 V -- 20 SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 2.7 < VDD < 3.6 V -- 20 SPI mode (SITP[1:0]=0,1), Internal clock mode (SPICKSEL[1:0] ≠0), 1.71 < VDD < 3.6 V -- 20 SPI mode (SITP[1:0]=0,1), Internal clock mode (SPICKSEL[1:0] ≠0), 2.7 < VDD < 3.6 V -- 20 fCKOUT Output clock frequency 1.71 < VDD < 3.6 V - - 20 DuCyCKOUT Output clock frequency duty cycle 1.71 < VDD < 3.6 V 45 50 55 % |
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