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STM32L4P5CE 数据表(PDF) 248 Page - STMicroelectronics |
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STM32L4P5CE 数据表(HTML) 248 Page - STMicroelectronics |
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248 / 311 page  Electrical characteristics STM32L4P5xx 248/311 DS12903 Rev 2 Asynchronous waveforms and timings Figure 48 through Figure 51 represent asynchronous waveforms and Table 101 through Table 108 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration: • AddressSetupTime(ADDSET) = 0x1 • AddressHoldTime(ADDHLD) = 0x1 • DataHoldTime(DATAHLD) = 0x1 (1THCLK for read operations and 2THCLK for write operations) • ByteLaneSetup(NBLSET)=0x1 • DataSetupTime(DATAST) = 0x1 (except for asynchronous NWAIT mode, DataSetupTime = 0x5) • BusTurnAroundDuration = 0x0 In all timing tables, the THCLK is the HCLK clock period. Figure 48. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms Data FMC_NE FMC_NBL[1:0] FMC_D[15:0] tv(BL_NE) t h(Data_NE) FMC_NOE Address FMC_A[25:0] tv(A_NE) FMC_NWE tsu(Data_NE) tw(NE) MS32753V1 w(NOE) t tv(NOE_NE) t h(NE_NOE) th(Data_NOE) t h(A_NOE) t h(BL_NOE) tsu(Data_NOE) FMC_NADV (1) t v(NADV_NE) tw(NADV) FMC_NWAIT tsu(NWAIT_NE) th(NE_NWAIT) |
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