MPC7410 datasheet(39/56 Pages) FREESCALE

39 / 56 page

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

Freescale Semiconductor

System Design Information

RP and RN are designed to be close to each other in value. Then, Z0 = (RP + RN)/2. Figure 24 describes the alternate

driver impedance measurement circuit.

Figure 24. Alternate Driver Impedance Measurement Circuit

Table 15 summarizes the signal impedance results. The driver impedance values were characterized at 0°, 65°, and

105°C. The impedance increases with junction temperature and is relatively unaffected by bus voltage.

8.6 Pull-Up Resistor Requirements

The MPC7410 requires pull-up resistors (1 k

Ω–5 kΩ) on several control pins of the bus interface to maintain the

control signals in the negated state after they have been actively negated and released by the MPC7410 or other bus

masters. These pins are: TS, ARTRY, SHDO, SHD1.

Four test pins also require pull-up resistors (100

Ω−1kΩ). These pins are CHK, L1_TSTCLK, L2_TSTCLK, and

LSSD_MODE. These signals are for factory use only and must be pulled up to OVDD for normal machine

operation.

If pull-down resistors are used to configure BVSEL or L2VSEL, the resistors should be less than 250

Ω (see Table

12). Because PLL_CFG[0:3] must remain stable during normal operation, strong pull-up and pull-down resistors

(1 k

Ω or less) are recommended to configure these signals in order to protect against erroneous switching due to

ground bounce, power supply noise or noise coupling.

In addition, CKSTP_OUT is an open-drain style output that requires a pull-up resistor (1 k

Ω–5 kΩ) if it is used by

the system. The CKSTP_IN signal should likewise be pulled up through a pull-up resistor (1 k

Ω–5 kΩ) to prevent

erroneous assertions of this signal.

During inactive periods on the bus, the address and transfer attributes may not be driven by any master and may,

therefore, float in the high-impedance state for relatively long periods of time. Since the MPC7410 must continually

monitor these signals for snooping, this float condition may cause excessive power draw by the input receivers on

Table 15. Impedance Characteristics

VDD = 1.8 V, OVDD = 2.5 V, Tj = 0° – 105°C

Impedance

Processor Bus

L2 Bus

Symbol

Unit

41.5–54.3

42.7–54.1

37.3–55.3

39.3–50.0

(L2)OVDD

BGA

Data

Vforce

OGND

MPC7410 数据表(PDF) 39 Page - Freescale Semiconductor, Inc

MPC7410 数据表(HTML) 39 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

数据表下载