MPC7410 datasheet(19/56 Pages) FREESCALE

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MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

Freescale Semiconductor

Electrical and Thermal Characteristics

The L2CLK_OUT timing diagram is shown in Figure 7.

Figure 7. L2CLK_OUT Output Timing Diagram

L2CLK_OUT output jitter

—

±150

—

±150

—

±150

Notes:

1. L2CLK outputs are L2CLK_OUTA, L2CLK_OUTB, and L2SYNC_OUT pins. The L2CLK frequency to core

frequency settings must be chosen such that the resulting L2CLK frequency and core frequency do not exceed their

respective maximum or minimum operating frequencies. The maximum L2CLK frequency will be system

dependent. L2CLK_OUTA and L2CLK_OUTB must have equal loading.

2. The nominal duty cycle of the L2CLK is 50% measured at midpoint voltage.

3. The DLL-relock time is specified in terms of L2CLKs. The number in the table must be multiplied by the period of

L2CLK to compute the actual time duration in ns. Relock timing is guaranteed by design and characterization.

4. The L2CR[L2SL] bit should be set for L2CLK frequencies less than 150 MHz. This adds more delay to each tap of

the DLL.

5. Allowable skew between L2SYNC_OUT and L2SYNC_IN.

6. Guaranteed by design and not tested. This output jitter number represents the maximum delay of one tap forward

or one tap back from the current DLL tap as the phase comparator seeks to minimize the phase difference between

L2SYNC_IN and the internal L2CLK. This number must be comprehended in the L2 timing analysis. The input jitter

on SYSCLK affects L2CLK_OUT and the L2 address/data/control signals equally and, therefore, is already

comprehended in the AC timing and does not have to be considered in the L2 timing analysis.

Table 9. L2CLK Output AC Timing Specifications (continued)

At recommended operating conditions (see Table 3)

Parameter

Symbol

400 MHz

450 MHz

500 MHz

Unit

Notes

Min

Max

Min

Max

Min

Max

VM = Midpoint Voltage (L2O

VDD/2)

L2CLK_OUTA

L2CLK_OUTB

L2 Differential Clock Mode

L2 Single-Ended Clock Mode

L2SYNC_OUT

tL2CLK

tCHCL

L2CLK_OUTA

tL2CR

tL2CF

L2CLK_OUTB

tL2CLK

tCHCL

L2SYNC_OUT

tL2CSKW

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