MPC7410 datasheet(6/56 Pages) FREESCALE

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MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

Freescale Semiconductor

Features

— L2 is fully pipelined to provide 128 bits per L2 clock cycle to the L1s.

— Up to eight outstanding, out-of-order, cache misses between dL1 and L2/bus

— Up to seven outstanding, out-of-order transactions on the bus

— Load folding to fold new dL1 misses into older, outstanding load and store misses to the same line

— Store miss merging for multiple store misses to the same line. Only coherency action taken (that is,

address only) for store misses merged to all 32 bytes of a cache line (no data tenure needed).

— Two-entry finished store queue and four-entry completed store queue between load/store unit and dL1

— Separate additional queues for efficient buffering of outbound data (castouts, write throughs, and so on)

from dL1 and L2

•

Bus interface

— MPX bus extension to 60x processor interface

— Mode-compatible with 60x processor interface

— 32-bit address bus

— 64-bit data bus

— Bus-to-core frequency multipliers of 2x, 2.5x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x, 8x, 9x

supported

— Selectable interface voltages of 1.8, 2.5, and 3.3 V

•

Power management

— Low-power design with thermal requirements very similar to MPC740 and MPC750

— Low-voltage processor core

— Selectable interface voltages can reduce power in output buffers

— Three static power saving modes: doze, nap, and sleep

— Dynamic power management

•

Testability

— LSSD scan design

— IEEE Std 1149.1™ JTAG interface

— Array built-in self test (ABIST)—factory test only

— Redundancy on L1 data arrays and L2 tag arrays

•

Reliability and serviceability

— Parity checking on 60x and L2 cache buses

MPC7410 数据表(PDF) 6 Page - Freescale Semiconductor, Inc

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