MPC8309CVMADDC datasheet(35/81 Pages) NXP

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MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3

Freescale Semiconductor

PCI

Figure 25 provides the AC test load for PCI.

Figure 25. PCI AC Test Load

Figure 26 shows the PCI input AC timing conditions.

Figure 26. PCI Input AC Timing Measurement Conditions

Figure 27 shows the PCI output AC timing conditions.

Figure 27. PCI Output AC Timing Measurement Condition

Input setup to clock

tPCIVKH

3.0

—

2, 4

Input hold from clock

tPCIXKH

—

2, 4

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing

(PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference

(K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset

(R) went high (H) relative to the frame signal (F) going to the valid (V) state.

2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.

3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

4. Input timings are measured at the pin.

Table 34. PCI AC Timing Specifications at 33 MHz (continued)

Parameter

Symbol1

Min

Max

Unit

Notes

Output

Z0 = 50 

OVDD/2

RL = 50 

tPCIVKH

CLK

Input

tPCIXKH

CLK

Output Delay

tPCKHOV

High-Impedance

tPCKHOZ

Output

tPCKHOX

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