ST7LITEU05 datasheet(27/115 Pages) STMICROELECTRONICS

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7.3 RESET SEQUENCE MANAGER (RSM)

7.3.1 Introduction

The reset sequence manager includes three RE-

SET sources as shown in Figure 16:

■

External RESET source pulse

■

Internal LVD RESET (Low Voltage Detection)

■

Internal WATCHDOG RESET

Note: A reset can also be triggered following the

detection of an illegal opcode or prebyte code. Re-

fer to Figure 16.

These sources act on the RESET pin and it is al-

ways kept low during the delay phase.

The RESET service routine vector is fixed at ad-

dresses FFFEh-FFFFh in the ST7 memory map.

The basic RESET sequence consists of 3 phases

as shown in Figure 15:

■

Active Phase depending on the RESET source

■

256 or 512 CPU clock cycle delay (see table

below)

■

RESET vector fetch

Caution: When the ST7 is unprogrammed or fully

erased, the Flash is blank and the RESET vector

is not programmed. For this reason, it is recom-

mended to keep the RESET pin in low state until

programming mode is entered, in order to avoid

unwanted behavior.

The 256 or 512 CPU clock cycle delay allows the

oscillator to stabilise and ensures that recovery

has taken place from the Reset state. The shorter

or longer clock cycle delay is automatically select-

ed depending on the clock source chosen by op-

tion byte after a reset or depending on the clock

source selected before entering Halt mode or

AWU from Halt mode:

Table 8. CPU clock cycle delay

The RESET vector fetch phase duration is 2 clock

cycles.

Figure 15. RESET Sequence Phases

Clock source

CPU clock

cycle delay

Internal RC oscillator

512

External clock (connected to CLKIN pin)

AWURC

256

RESET

Active Phase

INTERNAL RESET

256 OR 512 CLOCK CYCLES

FETCH

VECTOR

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