ST7LITEU05 datasheet(33/115 Pages) STMICROELECTRONICS

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INTERRUPTS (Cont’d)

EXTERNAL INTERRUPT CONTROL REGISTER

1 (EICR1)

Read/Write

Reset Value: 0000 0000 (00h)

Bits 7:6 = Reserved

Bits 5:4 = IS2[1:0] ei2 sensitivity

These bits define the interrupt sensitivity for ei2

according to Table 11.

Bits 3:2 = IS1[1:0] ei1 sensitivity

These bits define the interrupt sensitivity for ei1

according to Table 11.

Bits 1:0 = IS0[1:0] ei0 sensitivity

These bits define the interrupt sensitivity for ei0

according to Table 11.

Notes:

1. These 8 bits can be written only when the I bit in

the CC register is set.

2. Changing the sensitivity of a particular external

interrupt clears this pending interrupt. This can be

used to clear unwanted pending interrupts. Refer

to section “External interrupt function” on page 47.

3. Whatever the sensitivity configuration , ei2 can-

not exit the MCU from HALT, ACTIVE-HALT and

AWUFH modes when a falling edge occurs.

Table 11. Interrupt Sensitivity Bits

EXTERNAL INTERRUPT CONTROL REGISTER

2 (EICR2)

Read/Write

Reset Value: 0000 0000 (00h)

Bits 7:4 = Reserved

Bits 3:2 = IS4[1:0] ei4 sensitivity

These bits define the interrupt sensitivity for ei1

according to Table 11.

Bits 1:0 = IS3[1:0] ei3 sensitivity

These bits define the interrupt sensitivity for ei0

according to Table 11.

Notes:

1. These 8 bits can be written only when the I bit in

the CC register is set.

2. Changing the sensitivity of a particular external

interrupt clears this pending interrupt. This can be

used to clear unwanted pending interrupts. Refer

to section “External interrupt function” on page 47.

3. IS4[1:0] = 01 is the only safe configuration to

avoid spurious interrupt in HALT and AWUFH

modes.

IS21

IS20

IS11

IS10

IS01

IS00

ISx1 ISx0

External Interrupt Sensitivity

Falling edge & low level

Rising edge only

Falling edge only

Rising and falling edge

0000

IS41

IS40

IS31

IS30

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