M28F101 datasheet(8/23 Pages) STMICROELECTRONICS

8 / 23 page

Symbol

Alt

Parameter

Test Condition

M28F101

Unit

-120

-150

-200

VCC=5V

±10% VCC=5V±10% VCC=5V±10%

EPROM

Interface

EPROM

Interface

EPROM

Interface

Min

Max

Min

Max

Min

Max

tWHGL

Write Enable High to

Output Enable Low

µs

tAVAV

tRC

Read Cycle Time

E = VIL,G = VIL

120

150

200

tAVQV

tACC

Address Valid to

Output Valid

E=VIL,G = VIL

120

150

200

tELQX

(1)

tLZ

Chip Enable Low to

Output Transition

G= VIL

tELQV

tCE

Chip Enable Low to

Output Valid

G= VIL

120

150

200

tGLQX

(1)

tOLZ

Output Enable Low to

Output Transition

E= VIL

tGLQV

tOE

Output Enable Low to

Output Valid

E= VIL

tEHQZ

(1)

Chip Enable High to

Output Hi-Z

G= VIL

055

060

tGHQZ

(1)

tDF

Output Enable High to

Output Hi-Z

E= VIL

030

040

tAXQX

tOH

Address Transition to

Output Transition

E=VIL,G = VIL

Note: 1. Sampled only, not 100% tested

Table 9B. Read Only Mode AC Characteristics

((TA = 0 to 70

°C, –40 to 85 °C or –40 to 125 °C; 0V ≤ VPP ≤ 6.5V)

Erase and Erase Verify Modes. The memory is

erased by first Programming all bytes to 00h, the

Erase command then erases them to FFh. The

Erase Verify command is then used to read the

memory byte-by-byte for a content of FFh. The

Erase Mode is set-up by writing 20h to the com-

mand register. The write cycle is then repeated to

start the erase operation. Erasure starts on the

rising edge of W during this second cycle. Erase is

followed by an Erase Verify which reads an ad-

dressed byte.

Erase Verify Mode is set-up by writing A0h to the

command register and at the same time supplying

the address of the byte to be verified. The rising

edge of W during the set-up of the first Erase Verify

Mode stops the Erase operation. The following

read cycle is made with an internally generated

margin voltage applied; reading FFh indicates that

all bits of the addressed byte are fully erased. The

whole contents of the memory are verified by re-

peating the Erase Verify Operation, first writing the

set-up code A0h with the address of the byte to be

verified and then reading the byte contents in a

second read cycle.

8/23

M28F101

M28F101 数据表(PDF) 8 Page - STMicroelectronics

M28F101 数据表(HTML) 8 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

数据表下载

链接网址

M28F101 数据表(PDF) 8 Page - STMicroelectronics

M28F101 数据表(HTML) 8 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

数据表 下载

链接网址

数据表下载