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RC19302A00AGNT#BD0 数据表(PDF) 43 Page - Renesas Technology Corp |
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RC19302A00AGNT#BD0 数据表(HTML) 43 Page - Renesas Technology Corp |
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43 / 62 page  R31DS0210EU0106 Rev.1.06 Page 43 May 11, 2026 RC193xx Datasheet 4.5.15 LOW_LOW_DETECT CLKIN Low-Low Detect Enable Register. 4.5.16 RECEIVER_CONTROL CLKIN Configuration Register. 4 clk4_slewrate RW 0x1 CLK4 slew rate select. If B0xA[7]= 0 at power up, the SLEWRATE_SEL pin sets the default. After power up, the value can be changed via SMBus. If B0xA[7]= 1 at startup, default=1 0 = Slow slew rate 1 = Fast slew rate 3 clk3_slewrate RW 0x1 CLK3 slew rate select. If B0xA[7]= 0 at power up, the SLEWRATE_SEL pin sets the default. After power up, the value can be changed via SMBus. If B0xA[7]= 1 at startup, default=1 0 = Slow slew rate 1 = Fast slew rate 2 clk2_slewrate RW 0x1 CLK2 slew rate select. If B0xA[7]= 0 at power up, the SLEWRATE_SEL pin sets the default. After power up, the value can be changed via SMBus. If B0xA[7]= 1 at startup, default=1 0 = Slow slew rate 1 = Fast slew rate 1 clk1_slewrate RW 0x1 CLK1 slew rate select. If B0xA[7]= 0 at power up, the SLEWRATE_SEL pin sets the default. After power up, the value can be changed via SMBus. If B0xA[7]= 1 at startup, default=1 0 = Slow slew rate 1 = Fast slew rate 0 clk0_slewrate RW 0x1 CLK0 slew rate select. If B0xA[7]= 0 at power up, the SLEWRATE_SEL pin sets the default. After power up, the value can be changed via SMBus. If B0xA[7]= 1 at startup, default=1 0 = Slow slew rate 1 = Fast slew rate LOW_LOW_DETECT Bit Field Descriptions Bit Field Field Name Field Type Default Value Description 7:3 reserved RW 0x12 Reserved 2 low_low_det_enable RW 0x1 Enable low-low detect circuit on CLKIN0 and CLKIN1. Allows the device to detect a low-low condition on each CLKIN input and turn off the receiver. (Low- low is not a valid differential state). 0 = Disable 1 = Enable 1:0 reserved RW 0x0 Reserved RECEIVER_CONTROL Bit Field Descriptions Bit Field Field Name Field Type Default Value Description 7:4 reserved RW 0x0 Reserved 3 ac_in1 RW 0x0 AC-couple CLKIN1. When AC-coupling the input clock, set this bit to enable internal bias circuitry on the CLKIN1. This eliminates the need for external bias components on the CLKIN1 side of the AC-coupling capacitor. 0 = Disable internal bias (DC-coupled) 1 = Enable internal bias (AC-coupled) OUTPUT_SLEW_RATE_7_0 Bit Field Descriptions Bit Field Field Name Field Type Default Value Description |
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