R31DS0210EU0106 Rev.1.06

Page 20

May 11, 2026

RC193xx Datasheet

2.4.4

CLK (LP-HCSL) AC/DC Output Characteristics

Table 15. 85Ω CLK AC/DC Characteristics – Source-Terminated 100MHz PCIe Applications [1]

1. Standard high impedance load with CL = 2pF. See Test Loads.

Symbol

Parameter

Conditions

Minimum Typical Maximum Spec. Limit [2]

2. The specification limits are taken from either the PCI Express Base Specification 7.0 or from relevant x86 processor specifications, whichever is

more stringent.

Unit

VMAX

Absolute Max Voltage

Includes 300mV of

Overshoot (Vovs) [3][4]

3. Measured from single-ended waveform.

4. Defined as the maximum instantaneous voltage including overshoot.

Across all settings in this table at

100MHz.

-

-

1066

1150

mV

VMIN

Absolute Min Voltage

Includes -300mV of

Undershoot (Vuds) [3][5]

5. Defined as the minimum instantaneous voltage including undershoot.

-216

-

-

-300

VHIGH

Voltage High [3]

VHIGH set to 800mV.

703

837

960

-

mV

VLOW

Voltage Low [3]

-200

-91

26

-

VCROSS

Crossing Voltage (abs) [3]

[6][7]

6. Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling edge of REFCLK-.

7. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this

measurement.

VHIGH set to 800mV, scope

averaging off.

349

415

486

250 to 550

ΔVCROSS

Crossing Voltage (var) [3]

[6][8]

8. Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-. This is the maximum allowed variance in VCROSS

for any particular system.

-

26

30

140

dv/dt

Slew Rate [9][10]

9. Measured from differential waveform.

10. Measured from -150mV to +150mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be monotonic through

the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.

VHIGH set to 800mV, Fast slew rate,

scope averaging on.

1.9

2.8

3.9

1.8 to 4

V/ns

VHIGH set to 800mV, Slow slew

rate, scope averaging on.

1.6

2.4

3.4

1.5 to 3.5

ΔTR/F

Rise/Fall Matching [3][11]

11. Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a ±75mV window centered on the

median cross point where REFCLK+ rising meets REFCLK- falling. The median cross point is used to calculate the voltage thresholds the

oscilloscope is to use for the edge rate calculations. The Rise Edge Rate of REFCLK+ should be compared to the Fall Edge Rate of REFCLK-;

the maximum allowed difference should not exceed 20% of the slowest edge rate.

VHIGH set to 800mV. Fast slew rate.

-

2.9

12.5

20

%

ΔTR/F

Rise/Fall Matching [3][11]

VHIGH set to 800mV. Slow slew

rate.

-

2.7

10.5

VHIGH

Voltage High [3]

VHIGH set to 900mV.

774

920

1052

-

mV

VLOW

Voltage Low [3]

-215

-98

28

-

VCROSS

Crossing Voltage (abs) [3]

[6][7]

VHIGH set to 900mV, scope

averaging off.

371

445

526

300 to 600

ΔVCROSS

Crossing Voltage (var) [3]

[6][8]

-

26

31

140

dv/dt

Slew Rate [9][10]

VHIGH set to 900mV, Fast slew rate,

scope averaging on.

2.0

3.0

4.1

2 to 5

V/ns

VHIGH set to 900mV, Slow slew

rate, scope averaging on.

1.6

2.5

3.6

1.5 to 3.5

ΔTR/F

Rise/Fall Matching [3][11]

VHIGH set to 900mV. Fast slew rate.

-

3.1

11.7

20

%

ΔTR/F

Rise/Fall Matching [3][11]

VHIGH set to 900mV. Slow slew

rate.

-

3.5

15.0

20

%

tDC

Output Duty Cycle [9]

VT = 0V differential.

49.5

50.1

50.6

45 to 55

%