RC19302A00AGNT#BD0 datasheet(47/62 Pages) RENESAS

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R31DS0210EU0106 Rev.1.06

Page 47

May 11, 2026

RC193xx Datasheet

Figure 18. Direct-Coupled Double-Terminated HCSL

The RC193xx CLK outputs can directly drive AC-coupling capacitors without any source-termination components.

The differential input will require an input-dependent bias network. This network may or may not be internal to the

receiver. Refer to the receiver specification for detailed requirements. AC-coupling is used to connect the

RC193xx to other logic families such as LVDS, LVPECL, or CML. See AN-891 for examples.

Figure 19. AC-Coupled Differential Input with Bias Network

Table 33 contains values for the items in the above figures.

5.3.2

Internal CLK Source Termination Disabled (ZOUT_SEL_tri = M)

ZOUT_SEL_tri = M disables the internal source termination making the differential ZO = 34ohms. This setting is

used with receiver terminated loads to provide a higher CLK amplitude to the load than can be obtained with a

double terminated configuration. The minimum single-ended amplitude in this configuration targets ~500mV. See

Table 21 for detailed specifications. This setting is intended for ZDIF =100 ohm systems.

Figure 20. Direct-Coupled Receiver-Terminated HCSL

Figure 21. Alternate Direct-Coupled Receiver-Terminated Input

Table 33. Parameters for

Internal CLK Source Termination Enabled

ZOUT_SEL_tri

ZO (ohms)

ZDIF (ohms)

RP (ohms)

CAC (uF)

ZDIF /2

0.1

100

ZDIF /2

0.1

RC193xx

HCSL

Input

ZDIF

RC193xx

Differential

Input

CAC

ZDIF

Differential

Input

ZDIF

RC193xx

Differential

Input

RC193xx

ZDIF

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