| 数据搜索系统,热门电子元器件搜索 |
|
R5F10JBCAFP 数据表(PDF) 40 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
R5F10JBCAFP 数据表(HTML) 40 Page - Renesas Technology Corp |
|
40 / 142 page ![]() RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C) Page 40 of 138 R01DS0348EJ0140 Rev.1.40 Apr 26, 2024 (4) During communication at same potential (simplified SPI (CSI) mode) (slave mode, SCKp... external clock input) (TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCKp cycle time Note 5 tKCY2 4.0 V ≤ VDD ≤ 5.5 V 20 MHz < fMCK 8/fMCK ns fMCK ≤ 20 MHz 6/fMCK ns 2.7 V ≤ VDD ≤ 5.5 V 16 MHz < fMCK 8/fMCK ns fMCK ≤ 16 MHz 6/fMCK ns 2.4 V ≤ VDD ≤ 5.5 V 6/fMCK and 500 ns SCKp high-/low-level width tKH2, tKL2 4.0 V ≤ VDD ≤ 5.5 V tKCY2/2 − 7 ns 2.7 V ≤ VDD ≤ 5.5 V tKCY2/2 − 8 ns 2.4 V ≤ VDD ≤ 5.5 V tKCY2/2 − 18 ns SIp setup time (to SCKp ↑) Note 1 tSIK2 2.7 V ≤ VDD ≤ 5.5 V 1/fMCK+20 ns 2.4 V ≤ VDD ≤ 5.5 V 1/fMCK+30 ns SIp hold time (from SCKp ↑) Note 2 tKSI2 2.7 V ≤ VDD ≤ 5.5 V 1/fMCK+31 ns 2.4 V ≤ VDD ≤ 5.5 V 1/fMCK+31 ns Delay time from SCKp ↓ to SOp output Note 3 tKSO2 C = 30 pF Note 4 2.7 V ≤ VDD ≤ 5.5 V 2/fMCK+44 ns 2.4 V ≤ VDD ≤ 5.5 V 2/fMCK+75 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp ↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SOp output lines. 5. Transfer rate in the SNOOZE mode : MAX. 1 Mbps Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM number (g = 0, 3, 5, 7) 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01)) |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |