R5F10JBCAFP datasheet(49/142 Pages) RENESAS

49 / 142 page

RL78/G1C

2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)

Page 49 of 138

R01DS0348EJ0140 Rev.1.40

Apr 26, 2024

Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for

the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode

Remarks 1. Rb[

Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp)

load capacitance, Vb[V]: Communication line voltage

2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0),

g: PIM and POM number (g = 3, 5)

3. fMCK: Serial array unit operation clock frequency

(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,

n: Channel number (mn = 00)

4. This value is valid only when CSI00’s peripheral I/O redirect function is not used.

(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified SPI (CSI) mode) (master mode, SCKp...

internal clock output) (1/2)

(TA =

−40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

SCKp cycle time

tKCY1

≥ 4/fCLK 4.0 V ≤ VDD ≤ 5.5 V,

2.7 V

≤ Vb ≤ 4.0 V,

Cb = 30 pF, Rb = 1.4 k

300

2.7 V

≤ VDD < 4.0 V,

2.3 V

≤ Vb ≤ 2.7 V,

Cb = 30 pF, Rb = 2.7 k

500

2.4 V

≤ VDD < 3.3 V,

2.4 V

≤ Vb ≤ 2.0 V,

Cb = 30 pF, Rb = 5.5 k

1150

SCKp high-level width

tKH1

4.0 V

≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

Cb = 30 pF, Rb = 1.4 k

tKCY1/2

− 75

2.7 V

≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

Cb = 30 pF, Rb = 2.7 k

tKCY1/2

−

170

2.4 V

≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,

Cb = 30 pF, Rb = 5.5 k

tKCY1/2

−

458

SCKp low-level width

tKL1

4.0 V

≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

Cb = 30 pF, Rb = 1.4 k

tKCY1/2

− 12

2.7 V

≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

Cb = 30 pF, Rb = 2.7 k

tKCY1/2

− 18

2.4 V

≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,

Cb = 30 pF, Rb = 5.5 k

tKCY1/2

− 50

Cautions 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance)

mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port

output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input

buffer selected.

2. Use it with VDD

≥ Vb.

(Remarks are listed two pages after the next page.)

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