R5F10JBCAFP datasheet(28/142 Pages) RENESAS

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RL78/G1C

2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)

Page 28 of 138

R01DS0348EJ0140 Rev.1.40

Apr 26, 2024

Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is

fixed to VDD, or VSS. The following points apply in the HS (high-speed main) mode.

• The currents in the “TYP.” column do not include the operating currents of the peripheral modules.

• The currents in the “MAX.” column include the operating currents of the peripheral modules, except for

those flowing into the A/D converter, LVD circuit, USB 2.0 host/function module, I/O port, and on-chip

pull-up/pull-down resistors, and those flowing while the data flash memory is being rewritten.

In the subsystem clock operation, the currents in both the “TYP.” and “MAX.” columns do not include the

operating currents of the peripheral modules. However, in HALT mode, including the current flowing into

the RTC.

2. When high-speed on-chip oscillator and subsystem clock are stopped.

3. When high-speed system clock and subsystem clock are stopped.

4. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1

(Ultra-low power consumption oscillation).

5. When Operating frequency setting of option byte = 48 MHz. When fHOCO is divided by HOCODIV. When

RDIV[1:0] = 00 (divided by 2: default).

6. Relationship between operation voltage width, operation frequency of CPU and operation mode is as

below.

HS (high-speed main) mode:

2.7 V

≤ VDD ≤ 5.5 V@1 MHz to 24 MHz

2.4 V

≤ VDD ≤ 5.5 V@1 MHz to 16 MHz

Remarks 1. fHOCO: High-speed on-chip oscillator clock frequency (Max. 48 MHz)

2. fIH:

Main system clock source frequency obtained by dividing the high-speed on-chip oscillator clock

by 2, 4, or 8 (Max. 24 MHz)

3. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system

clock frequency)

4. fPLL: PLL oscillation frequency

5. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)

6. fCLK: CPU/peripheral hardware clock frequency

7. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25

°C.

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