R5F10JBCAFP datasheet(16/142 Pages) RENESAS

16 / 142 page

RL78/G1C

1. OUTLINE

Page 16 of 138

R01DS0348EJ0140 Rev.1.40

Apr 26, 2024

(2/2)

Item

32-pin

48-pin

R5F10JBC

R5F10KBC

R5F10JGC

R5F10KGC

Clock output/buzzer output

•

2.93 kHz, 5.86 kHz, 11.7 kHz, 1.5 MHz, 3 MHz, 6 MHz, 12 MHz

(Main system clock: fMAIN = 24 MHz operation)

•

256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768

kHz

(Subsystem clock: fSUB = 32.768 kHz operation)

8/10-bit resolution A/D converter

8 channels

9 channels

Serial interface

Simplified SPI (CSI): 2 channels/UART: 1 channel/simplified I2C: 2 channels

I2C bus

1 channel

USB

Host controller

2 channels

−

2 channels

−

Function controller

1 channel

Multiplier and

divider/multiply-accumulator

• Multiplier:

16 bits

× 16 bits = 32 bits (Unsigned or signed)

• Divider:

32 bits

÷ 32 bits = 32 bits (Unsigned)

• Multiply-accumulator:16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed)

DMA controller

2 channels

Vectored

interrupt

sources

Internal

External

Key interrupt

−

Reset

• Reset by RESET pin

• Internal reset by watchdog timer

• Internal reset by power-on-reset

• Internal reset by voltage detector

• Internal reset by illegal instruction execution Note

• Internal reset by RAM parity error

• Internal reset by illegal-memory access

Power-on-reset circuit

• Power-on-reset:

1.51 V (TYP.)

• Power-down-reset:

1.50 V (TYP.)

Voltage detector

2.45 V to 4.06 V (9 stages)

On-chip debug function

Provided

Power supply voltage

VDD = 2.4 to 5.5 V

Operating ambient temperature

TA =

−40 to +85 °C (A: Consumer applications), TA = −40 to +105°C (G: Industrial applications)

Note The illegal instruction is generated when instruction code FFH is executed.

Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip

debug emulator.

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